Improve the performance and reliability of synchronous digital integrated circuits with this anthology of key literature on the design and analysis of clock distribution networks for VLSI based computer and signal processing systems. Beginning with an extensive tutorial overview and bibliography, this all in one source offers substantive coverage of the most relevant issues related to the design of clock distribution networks for application to high performance synchronous design. Related topics include clock skew; automated layout of clock nets; distributed buffet and interconnect delays; clock distribution design of structured custom VLSI circuits; wafer scale integration; systolic arrays; globally asynchronous, locally synchronous systems; microwave issues; low power clocking techniques; process insensitive circuits; deterministic and probabilistic delay models; system timing specifications; clock distribution networks of well known circuits and future research in clock distribution networks. The material presented in Clock Distribution Networks in VLSI Circuits and Systems will be valuable to anyone with an interest in synchronous integrated circuits, computer design, or signal processing implementation issues.

. . . ????????????????????????????????? ????????????? ????????????,????? ???? ??????????? ???????????????????? ???. THUCYDIDIS HISTORIAE IV:108 C. Hude ed. , Teubner, Lipsiae MCMXIII ???????????,????? ??,? ????????????????? ???????????????????? ?????? ?????? ?????? ??? ????????? ??? ?’ ?????????? ??’ ?????????? ? ??????? ??? ????????????? ???????. ???????????????????:108 ???????????? ?????????????????????? ?. ?????????????. ????????????,????? It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject. Thucydides (the Peloponnesian War Part I), IV:108 Thomas Hobbes Trans. , Sir W. Molesworth ed. In The English Works of Thomas Hobbes of Malmesbury, Vol. VIII I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors - hibited highly innovative clocking systems, always worthy of ISSCC/JSSC publi- tions and for a while Alpha processors were leading the industry in terms of clock performance. I had huge shoes to ?ll. Obviously, I was overwhelmed, confused and highly con?dent that I would drag the entire project down.

A number of fundamental topics in the field of high performance clock distribution networks is covered in this book. High Performance Clock Distribution Networks is composed of ten contributions from authors at academic and industrial institutions. Topically, these contributions can be grouped within three primary areas. The first topic area deals with exploiting the localized nature of clock skew. The second topic area deals with the implementation of these clock distribution networks, while the third topic area considers more long-range aspects of next-generation clock distribution networks. High Performance Clock Distribution Networks presents a number of interesting strategies for designing and building high performance clock distribution networks. Many aspects of the ideas presented in these contributions are being developed and applied today in next-generation high-performance microprocessors.

The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.

With the advancement of nanometer scale processes in CMOS technologies, the demand for high performance VLSI systems continues to grow exponentially. The performance of a microprocessor is influenced by its clock distribution network. Clock skew penalizes the overall performance of the system. The task of minimizing clock skew in clock distribution networks continues to be critical in high speed circuits to maximize system performance. The objective of this research is to design a low skew clock distribution network by inserting Delay-Locked Loops with buffers along different clock paths of the clock distribution network. The delay-locked loops use delay lines which produce significantly lower skew and jitter than phase-locked loops. Clock skew can be reduced by employing DLLs in several appropriate places of the clock distribution network. The approach of distributing DLLs in a clock distribution network requires additional area but greatly improves the performance of VLSI systems.

"The exponential growth in the computational capabilities of humankind cannot be sustained without innovative design methodologies to manage the immense complexity of VLSI systems. To facilitate cooperation across diverse disciplines, the IC design process is composed of multiple abstraction layers. Decomposition of the VLSI process into discrete components enables the automation of manually intractable circuit design tasks. Graph theory plays an important role in electronic design automation (EDA) by providing powerful and versatile algorithms to tackle a variety of VLSI system design issues at each layer of abstraction. In this dissertation, a diverse spectrum of graph theory applications in the design of VLSI circuits is discussed, ranging from coloring-based register allocation at the register transfer layer to tree-based floorplanning at the physical layer. Graph-based synthesis of VLSI power and clock distribution networks is an emphasis of this dissertation. By exploiting the duality between a random walk within a graph and resistive electrical networks, an efficient algorithm for analyzing arbitrarily large power grids is proposed. Based on this model, a set of voltage regulators are efficiently distributed within a power grid, drastically improving the power integrity of a synthesized integrated system. To facilitate the development of power distribution networks at early stages of the system design process, the Smart Power ROUTing (SPROUT) tool for power delivery exploration and prototyping at the board level is proposed. By converting the physical layout of a power network into a graph, prototypical physical layouts are efficiently created. From an analysis of these prototypes, the power network characteristics can be accurately predicted during early stages of the design process. Graph theory is applied to the synthesis of clock distribution networks for super-conductive single flux quantum (SFQ) integrated circuits. A clock skew scheduling algorithm, originally developed for CMOS circuits, is adapted to synchronize SFQ circuits. Based on a schedule of clock arrival times produced for SFQ systems, a clock tree topology is determined. Applying a proxy graph technique, a clock tree layout based on the clock tree topology is synthesized."--Pages xx-xxi.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis. The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.