Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. This detailed book covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. Many practical circuit examples are included to demonstrate the interplay between technology, interconnect and circuit design.

This book focuses on the modelling methodology of microstrip interconnects, discussing various structures of single-input multiple-output (SIMO) tree interconnects for signal integrity (SI) engineering. Further, it describes lumped and distributed transmission line elements based on single-input single-output (SIMO) models of symmetric and asymmetric trees, and investigates more complicated phenomenon, such as interbranch coupling. The modelling approaches are based on the analytical methods using the Z-, Y- and T-matrices. The established method enables the S-parameters and voltage transfer function of SIMO tree to be determined. Providing illustrative results with frequency and time domain analyses for each tree interconnect structure, the book is a valuable resource for researchers, engineers, and graduate students in fields of analogue, RF/microwave, digital and mixed circuit design, SI and manufacturing engineering.

The two volume set LNCS 7439 and 7440 comprises the proceedings of the 12th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2012, as well as some workshop papers of the CDCN 2012 workshop which was held in conjunction with this conference. The 40 regular paper and 26 short papers included in these proceedings were carefully reviewed and selected from 156 submissions. The CDCN workshop attracted a total of 19 original submissions, 8 of which are included in part II of these proceedings. The papers cover many dimensions of parallel algorithms and architectures, encompassing fundamental theoretical approaches, practical experimental results, and commercial components and systems.

Biopotential Readout Circuits for Portable Acquisition Systems describes one of the main building blocks of such miniaturized biomedical signal acquisition systems. The focus of this book is on the implementation of low-power and high-performance integrated circuit building blocks that can be used to extract biopotential signals from conventional biopotential electrodes. New instrumentation amplifier architectures are introduced and their design is described in detail. These amplifiers are used to implement complete acquisition demonstrator systems that are a stepping stone towards practical miniaturized and low-power systems.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book.

Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied. Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.