This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.

This book is based on the 18 presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This book is based on the 18 presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This book discusses both architecture and circuit design aspects of Delta-Sigma A/D converters, with a special focus on multi-bit implementations. The emphasis is on high-speed high-resolution converters in CMOS for ADSL applications, although the material can also be applied for other specification goals and technologies.

This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Wireless Receiver Architectures and Design presents the various designs and architectures of wireless receivers in the context of modern multi-mode and multi-standard devices. This one-stop reference and guide to designing low-cost low-power multi-mode, multi-standard receivers treats analog and digital signal processing simultaneously, with equal detail given to the chosen architecture and modulating waveform. It provides a complete understanding of the receiver's analog front end and the digital backend, and how each affects the other. The book explains the design process in great detail, starting from an analysis of requirements to the choice of architecture and finally to the design and algorithm development. The advantages and disadvantages of each wireless architecture and the suitability to a standard are given, enabling a better choice of design methodology, receiver lineup, analog block, and digital algorithm for a particular architecture. Whether you are a communications engineer working in system architecture and waveform design, an RF engineer working on noise and linearity budget and line-up analysis, a DSP engineer working on algorithm development, or an analog or digital design engineer designing circuits for wireless transceivers, this book is your one-stop reference and guide to designing low-cost low-power multi-mode multi-standard receivers. The material in this book is organized and presented to lead you from applied theory to practical design with plenty of examples and case studies drawn from modern wireless standards. - Provides a complete description of receiver architectures together with their pros and cons, enabling a better choice of design methodology - Covers the design trade-offs and algorithms between the analog front end and the digital modem – enabling an end-to-end design approach - Addresses multi-mode multi-standard low-cost, low-power radio design – critical for producing the applications for Smart phones and portable internet devices