Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks

This book constitutes the thoroughly refereed post-conference proceedings of the 19th and 20th International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2015 and 2016, held respectively in Hyderabad, India, on May 26, 2015 and in Chicago, IL, USA, on May 27, 2016. The 14 revised full papers presented (7 papers in 2015 and 7 papers in 2016) were carefully reviewed and selected from 28 submissions (14 in 2015 and 14 in 2016). The papers cover the following topics: parallel scheduling raising challenges multiple levels of abstractions; node level parallelism; minimization of energy consumption in task migration within a many-core chip; task replication in real-time scheduling context; data-driven approach to schedule GPU load; the use of lock-free data structures in OS scheduler; the influence between user behaviour (think time, more precisely) and parallel scheduling; Evalix, a predictor for job resource consumption; sophisticated and realistic simulation; space-filling curves leading to better scheduling of large-scale computers; discussion of real-life production experiences.

This book constitutes the proceedings of the 30th International Conference on Architecture of Computing Systems, ARCS 2017, held in Vienna, Austria, in April 2017. The 19 full papers presented in this volume were carefully reviewed and selected from 42 submissions. They were organized in topical sections entitled: resilience; accelerators; performance; memory systems; parallelism and many-core; scheduling; power/energy.

This book presents new concepts, techniques and promising programming models for designing software for chips with "many" (hundreds to thousands) processor cores. Given the scale of parallelism inherent to these chips, software designers face new challenges in terms of operating systems, middleware and applications. This will serve as an invaluable, single-source reference to the state-of-the-art in programming many-core chips. Coverage includes many-core architectures, operating systems, middleware, and programming models.

A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.