FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity. The architecture of an FPGA is very regular. It is relatively easy to design a highly optimized tile, with consideration of various manufacturing related issues, and then to replicate it many times across the chip. The configurability of FPGAs also enables yield improvement and defect tolerance. However, FPGAs are still facing serious challenges in terms of delay, power consumption, and logic density compared to ASICs. FPGA is estimated to be over twenty times less efficient in logic density, over three times worse in delay, and over ten times higher in power consumption compared to a functionally equivalent ASIC. One promising way to improve FPGA performance is to incorporate three-dimensional (3D) integration, which increases the number of active layers and optimizes the interconnect network vertically. Another solution is to apply novel nanoelectronic materials (nanomaterials) and devices. This dissertation introduces three novel reconfigurable architectures, named 3D nFPGA, FPCNA (field programmable carbon nanotube array), and NEM FPGA (nanoelectromechanical FPGA), which utilize 3D integration techniques and new nanoscale materials synergistically. Customized CAD flows that consider process variation have been developed for different architectures to evaluate their potential performances. Also described is a 3D variation aware routing flow, which is an essential tool for future 3D FPGA architecture exploration. 3D nFPGA is based on CMOS (complementary metal-oxide-semiconductor) and nano hybrid techniques that incorporate nanomaterials such as nanowire crossbars and carbon nanotube bundles into the CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4©7 footprint reduction comparing to the traditional CMOS-based 2D FPGAs. The performance and power of 3D nFPGA driven by the 20 largest MCNC (microelectronics center of North Carolina) benchmarks have been evaluated. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6©7 with a small power overhead compared to the traditional 2D FPGA. FPCNA includes lookup tables created entirely from continuous carbon nanotube (CNT) ribbons. To determine the performance of the building blocks, variation aware physical design tools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian and non-Gaussian random variables. A 2.75©7 performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5©7 footprint reduction compared to a baseline FPGA. 3D NEM FPGA is the architecture that utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. This proposed architecture has unique features including a hybrid CMOS-NEM FPGA lookup table (LUT) and configurable logic block (CLB), NEM-based switch block (SB) and connection block (CB), and face-to-face 3D stacking. This architecture also has a built-in feature called direct link, which takes advantage of the short vertical wire length provided by 3D stacking to further enhance performance. An overall 46.3% critical path delay reduction has been observed compared to its CMOS counterpart. To maximize the potential performance gain of 3D integrated circuit architectures, an SSTA engine was developed to deal with both uncorrelated and correlated variations in 3D FPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physical design tool TPR as a base, a new 3D routing algorithm is developed, which improves the average performance of two-layer designs by over 22% and three-layer designs by over 27%.

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and professionals alike.

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools. Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert. In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues. Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.

In this work, the benefits of using 3-D integration in the fabrication of Field Programmable Gate Arrays (FPGAs) are analyzed. A CAD tool has been developed to specify 3-dimensional FPGA architectures and map RTL descriptions of circuits to these 3-D FPGAs. The CAD tool was created from the widely used Versatile Place and Route (VPR) CAD tool for 2-D FPGAs. The tool performs timing-driven placement of logic blocks in the 3-dimensional grid of the FPGA using a two-stage Simulated Annealing (SA) process. The SA algorithm in the original VPR tool has been modified to focus more directly on minimizing the critical path delay of the circuit and hence maximizing the performance of the mapped circuit. After placing the logic blocks, the tool generates a Routing-Resource graph from the 3-D FPGA architecture for the VPR router. This allows the efficient Pathfinder-based VPR router to be used without any modification for the 3-D architecture. The CAD tool that was developed for mapping circuits to the fabricated 3-D FPGA is also used for exploring the design space for the 3-D FPGA architecture. A significant contribution of this work is a dual-interconnect architecture for the 3-D FPGA which has parasitic capacitance comparable to 2-D FPGAs. The nets routed in a 3-D FPGA are divided into intra-layer nets and inter-layer nets, which are routed on separate interconnect systems. This work also proposes a technique called I/O pipelining which pipelines the primary inputs and outputs of the FPGA through unused registers. This 3-D architecture and I/O pipelining technique have not been found in any of the works proposed so far, in the area of 3-D FPGA design. It is shown that the Dual-Interconnect I/O pipelined 3-D FPGA on an average achieves 43% delay improvement and in the best case, up to 54% for the MCNC'91 benchmark circuits.

This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS. While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.