Abstract: "Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented some or all of their cache coherence protocols in software. One way to exploit the flexibility of this software is to tailor a coherence protocol to match an application's communication patterns and memory semantics. This paper presents evidence that this approach can lead to large performance improvements. It shows that application-specific protocols substantially improved the performance of three application programs -- appbt, em3d, and barnes -- over carefully tuned transparent shared memory implementations. The speed-ups were obtained on Blizzard, a fine-grained DSM system running on a 32-node Thinking Machines CM-5."

Clusters of workstations/PCs connected by o?-the-shelf networks have become popular as a platform for cost-e?ective parallel computing. Hardware and so- ware technological advances have made this network-based parallel computing platform feasible. A large number of research groups from academia and industry are working to enhance the capabilities of such a platform, thereby improving its cost-e?ectiveness and usability. These developments are facilitating the mig- tion of many existing applications as well as the development of new applications on this platform. Continuing in the tradition of the two previously successful workshops, this 3rd Workshop on Communication, Architecture and Applications for Netwo- based Parallel Computing (CANPC’99) has brought together researchers and practitioners working in architecture, system software, applications and perf- mance evaluation to discuss state-of-the-art solutions for network-based parallel computing systems. This workshop has become an excellent forum for timely dissemination of ideas and healthy interaction on topics at the cutting edge in cluster computing technology. Each submitted paper underwent a rigorous review process, and was assigned to at least 3 reviewers, including at least 2 program committee members. Each paper received at least 2 reviews, most received 3 and some even had 4 reviews.

The papers present in this text survey both distributed shared memory (DSM) efforts and commercial DSM systems. The book discusses relevant issues that make the concept of DSM one of the most attractive approaches for building large-scale, high-performance multiprocessor systems. The authors provide a general introduction to the DSM field as well as a broad survey of the basic DSM concepts, mechanisms, design issues, and systems. The book concentrates on basic DSM algorithms, their enhancements, and their performance evaluation. In addition, it details implementations that employ DSM solutions at the software and the hardware level. This guide is a research and development reference that provides state-of-the art information that will be useful to architects, designers, and programmers of DSM systems.

This book presents the refereed proceedings of the Second International Workshop on Applied Parallel Computing in Physics, Chemistry and Engineering Science, PARA'95, held in Lyngby, Denmark, in August 1995. The 60 revised full papers included have been contributed by physicists, chemists, and engineers, as well as by computer scientists and mathematicians, and document the successful cooperation of different scientific communities in the booming area of computational science and high performance computing. Many widely-used numerical algorithms and their applications on parallel computers are treated in detail.

This book presents the thoroughly refereed post-workshop proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing, LCPC'96, held in San Jose, California, in August 1996. The book contains 35 carefully revised full papers together with nine poster presentations. The papers are organized in topical sections on automatic data distribution and locality enhancement, program analysis, compiler algorithms for fine-grain parallelism, instruction scheduling and register allocation, parallelizing compilers, communication optimization, compiling HPF, and run-time control of parallelism.