Low availability, high cost, and poor performance of radiation hardened (rad-hard) equipment has driven the market to rely on commercial-off- the-shelf (COTS) equipment for the computing needs of today's spacecraft. This thesis describes the tailoring of a COTS embedded real-time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation- induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware design used for this research is an acceptable fault-tolerant design candidate for the main processor for space-based applications. We found that a COTS embedded real-time operating system could be tailored to support the TMR hardware. The HCI accepts serial data from the TMR, correctly identifies the source of the error, allows for processor mode selection and provides system- and board-level reset capabilities. The tailored operating system combined with the HCI is a viable software imp- lementation to support hardware-based fault-tolerant computing in a space environment.

Comprehensive coverage of all aspects of space application oriented fault tolerance techniques • Experienced expert author working on fault tolerance for Chinese space program for almost three decades • Initiatively provides a systematic texts for the cutting-edge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge • Presents fundamental and advanced theories and technologies in a logical and easy-to-understand manner • Beneficial to readers inside and outside the area of space applications

The purpose of this thesis is to analyze and determine the feasibility of implementing a fault tolerant computing system that is able to function in the presence of radiation induced Single Event Upsets (SEU) by using the Triple Modular Redundancy (TMR) technique with 64-bit Commercial-Off-The- Shelf (COTS) microprocessors. Due to the radiation environment in space, electronic devices must be designed to tolerate the radiation effects. While there are radiation-hardened devices that can tolerate radiation effects, they offer lower performance and higher cost than COTS devices. On the other hand, COTS devices offer lower cost, orders of magnitude higher performance, shorter design time and better software availability and compatibility. However, COTS devices are susceptible to the radiation effects. In order to use COTS devices in space environment, a fault tolerance technique such as TMR needs to be implemented. This thesis presents the design and analysis of a TMR 64-bit COTS microprocessor implementation. The system incorporates three 64-bit microprocessors, the memory system including SRAM and PROM memory modules and the programmable logic devices that are used to implement the IMR technique. The validity of the design is verified by the timing analysis conducted on read and write operations.

For the editors of this book, as well as for many other researchers in the area of fault-tolerant computing, Dr. William Caswell Carter is one of the key figures in the formation and development of this important field. We felt that the IFIP Working Group 10.4 at Baden, Austria, in June 1986, which coincided with an important step in Bill's career, was an appropriate occasion to honor Bill's contributions and achievements by organizing a one day "Symposium on the Evolution of Fault-Tolerant Computing" in the honor of William C. Carter. The Symposium, held on June 30, 1986, brought together a group of eminent scientists from all over the world to discuss the evolu tion, the state of the art, and the future perspectives of the field of fault-tolerant computing. Historic developments in academia and industry were presented by individuals who themselves have actively been involved in bringing them about. The Symposium proved to be a unique historic event and these Proceedings, which contain the final versions of the papers presented at Baden, are an authentic reference document.

This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

With spacecraft designs placing more emphasis on reduced cost, faster design time, and higher performance, it is easy to understand why more commercial-off-the-shelf (COTS) devices are being used in space based applications. The COTS devices offer spacecraft designers shorter design-to- orbit times, lower system costs, orders of magnitude better performance, and a much better software availability than their radiation hardened (radhard) counterparts. The major drawback to using COTS devices in space is their increased susceptibility to the effects of radiation, single event upsets (SEUs) in particular. This thesis will focus on the implementation of a fault tolerant computer system. The hardware design presented here has two different benefits. First, the system can act as a software testbed, which allows testing of software fault tolerant techniques in the presence of radiation induced SEUs. This allows the testing of the software algorithms in the environment they were designed to operate in without the expense of being placed in orbit. Additionally, the design can be used as a hybrid fault tolerant computer system. By combining the masking ability of the hardware with supporting software, the system can mask out and reset processor errors in real time. The design layout will be presented using OrCAD schematics.