Split manufacturing is a technique that allows manufacturing the transistor-level and lower metal layers of an IC at a high-end, untrusted foundry, while manufacturing only the higher metal layers at a smaller, trusted foundry. Using split manufacturing is only viable if the untrusted foundry cannot reverse engineer the higher metal layer connections (and thus the overall IC design) from the lower layers. This work begins with a study of the effectiveness of proximity attack as a key step to reverse engineer a design at the untrusted foundry. We propose and study different proximity attacks based on how a set of candidates are defined for each broken connection. The attacks use both placement and routing information along with factors which capture the router's behavior such as per-layer routing congestion. Our studies are based on designs having millions of nets routed across 9 metal layers and significant layer-by-layer wire size variation. Our results show that a common, Hamming Distance-based proximity attack seldom achieves a match rate over 5%. But our proposed attack yields a relatively-small list of candidates which often contains the correct match. We also propose a procedure to artificially insert routing blockages in a design at a desired split level, without causing any area overhead, in order to trick the router to make proximity-based reverse engineering significantly more challenging. This work goes on to analyze the security of split manufacturing using machine learning. We consider many types of layout features for machine learning including those obtained from placement, routing, and cell sizes. For the top split layer, we demonstrate dramatically better results in proximity attack compared to the same proximity attack without machine learning. We analyze the ranking of features used by machine learning and show the importance of how features vary when moving to the lower layers. Since the runtime of our basic machine learning becomes prohibitively large for lower layers, we propose novel techniques to make it scalable with little sacrifice in effectiveness of the attack. This work concludes by proposing a routing-based defense mechanism against the proximity attack. Our model is able to simultaneously generate multiple routing solutions which exhibit a trade off between the enhanced security versus degradation in wirelength. This means the generated solutions are Pareto-optimal with respect to each other such that for example, for a desired security, one solution is always best in terms of wirelength overhead, or for a desired allowable wirelength overhead, one solution always has the highest security. Our algorithm guarantees its process does not generate overflow of routing resources and gives flexibility to the designer to eventually select one of these generated solutions based on a desired level of security or tolerable wirelength overhead. This addresses an issue common in prior work, where a designer lacks control over a routing obfuscation technique's wirelength overhead. The effectiveness of our algorithm is demonstrated with experiments using the ISPD'11 benchmarks featuring up to two million nets.

Globalization of the integrated circuit (IC) supply chains led to many potential vulnerabilities. Several attack scenarios can exploit these vulnerabilities to reverse engineer IC designs or to insert malicious trojan circuits. Split manufacturing refers to the process of splitting an IC design into multiple parts and fabricating these parts at two or more foundries such that the design is secure even when some or all of those foundries are potentially untrusted. Realizing its security benefits, researchers have proposed split fabrication methods for 2D, 2.5D, and the emerging 3D ICs. Both attack methods against split designs and defense techniques to thwart those attacks while minimizing overheads have steadily progressed over the past decade. This book presents a comprehensive review of the state-of-the-art and emerging directions in design splitting for secure split fabrication, design recognition and recovery attacks against split designs, and design techniques to defend against those attacks. Readers will learn methodologies for secure and trusted IC design and fabrication using split design methods to protect against supply chain vulnerabilities.

This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange of obfuscation keys- arguably the most critical element of hardware obfuscation.

This book provides a comprehensive coverage of hardware security concepts, derived from the unique characteristics of emerging logic and memory devices and related architectures. The primary focus is on mapping device-specific properties, such as multi-functionality, runtime polymorphism, intrinsic entropy, nonlinearity, ease of heterogeneous integration, and tamper-resilience to the corresponding security primitives that they help realize, such as static and dynamic camouflaging, true random number generation, physically unclonable functions, secure heterogeneous and large-scale systems, and tamper-proof memories. The authors discuss several device technologies offering the desired properties (including spintronics switches, memristors, silicon nanowire transistors and ferroelectric devices) for such security primitives and schemes, while also providing a detailed case study for each of the outlined security applications. Overall, the book gives a holistic perspective of how the promising properties found in emerging devices, which are not readily afforded by traditional CMOS devices and systems, can help advance the field of hardware security.

This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade. The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs). Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat. · Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; · Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; · Provides step-by-step solutions for detecting different types of counterfeit ICs; · Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC detection and avoidance, for industry and government.

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.