Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and even single-chip radios. This book offers a quick grasp of emerging research topics in RF integrated circuit design and their potential applications, with brief introductions to key topics followed by references to specialist papers for further reading. All of the chapters, compiled by editors well known in their field, have been authored by renowned experts in the subject. Each includes a complete introduction, followed by the relevant most significant and recent results on the topic at hand. This book gives researchers in industry and universities a quick grasp of the most important developments in analog and RF integrated circuit design. - Emerging research topics in RF IC design and its potential application - Case studies and practical implementation examples - Covers fundamental building blocks of a cellular base station system and satellite infrastructure - Insights from the experts on the design and the technology trade-offs, the challenges and open questions they often face - References to specialist papers for further reading

Mixers are a vital part of any transceiver architecture, and their performance is critical to achieving overall specifications. Although the basic operation is, in principle, a simple multiplication, in reality the circuit level implementation must be tailored to the specific function in the signal chain, and the technology being used. Starting from some of the basic principles, this chapter aims to identify the physical origins of noise and linearity issues, and lay out the design constraints and choices for the mixer function in a modern fully integrated transceiver. With the current prevalence of CMOS, passive mixers are examined as well as the classical current steering active type and their suitability in receive and transmit functions is considered. Enhanced passive and active mixers are also examined, exploiting the I and Q signal path available in complex receiver architectures.

This chapter presents one of the first integrated Ku-band downconverters with PLL frequency synthesizer that has widely penetrated the market of low noise blocks (LNBs) for reception of satellite television. It starts with a brief description of the general architecture of a LNB and a presentation of the main requirements for the integrated downconverter and frequency synthesizer. The architecture of the integrated circuit and the design of its building blocks are then presented and discussed in detail. The emphasis is put on the design choices made in the downconverter and the synthesizer for competing in cost and performance with discrete implementations at minimal power consumption. By the end of the chapter, measurement results are reported that illustrate the downconverter performance alone or within a demonstration LNB.

Time-to-digital converter (TDC) circuits are a key component for achieving high-performance digital phase-locked loops (PLLs) which offer lower area and greater flexibility than their analog PLL counterparts. This chapter focuses on a recently developed TDC architecture known as the gated ring oscillator (GRO) which offers first-order shaping of its quantization noise and delay stage mismatch. To provide context for the GRO discussion, background on general TDC implementation techniques is described along with key performance issues related to digital frequency synthesizers. The GRO concept is then presented, followed by implementation details and measured results. Finally, recent variations on the GRO concept are described such as a MASH TDC structure which achieves higher-order noise shaping and a switched ring oscillator (SRO) TDC which improves robustness to dead zones encountered by the GRO TDC.

This chapter discusses the practical application of RF digital-to-analog converters (RF DACs) to communication systems such as cable distribution, wireless communications infrastructure (WIFR) base stations, wireless backhaul, and other such systems. The key specifications that are driving the development of RF DAC technology are reviewed, as are some common radio architectures used to implement those systems. Challenges associated with the design of RF DACs are described, and some trade-offs and possible solutions are discussed. Design considerations of the package and the printed circuit board (PCB) design are reviewed. Measured results of an RF DAC suitable for cable head-end transmitters are presented. The features and performance of RF DACs provide an enabling solution for “Software Defined Radio” (SDR) systems targeted toward multi-carrier, multi-band, multi-standard radio transmitters.

This chapter provides an overview of design techniques and system aspects relevant to the application of high-speed pipelined ADCs in wireless base transceiver stations (BTS). The discussion begins with a derivation of typical ADC specifications for the receive path of a multi-carrier BTS system. Next, we investigate issues pertaining to the interface between the ADC and its driving circuitry, including complications that arise with sample-and-hold-amplifier-less (SHA-less) ADC frontends. Lastly, we summarize recent research results that look into the digital linearization of dynamic nonlinearities at the ADC’s frontend.

In less than one decade after their introduction into radio-frequency applications, digital fractional-N phase-locked loops (PLLs) have become a relevant topic in microelectronic research and a practical solution for products. In addition to the well-known advantages, such as their silicon area occupation scaling as technology node and their easier portability to new nodes, digital PLLs enable easy and low-cost implementation of calibration techniques, which substantially reduce spurious tones and remove other major analog impairments. In wideband PLLs, the ultimate level of spur performance is often bounded by the time resolution and the linearity of the time-to-digital converter within the digital PLL. Methods for mitigating its nonlinearity such as those based on element randomization and large-scale dithering are discussed. The use of fractional-N dividers based on digital-to-time converters, as a means to relax the design of the time-to-digital converter, is also reviewed. This concept is extended to the limit case of a single-bit time-to-digital converter, which provides best PLL noise–power trade-off with good spur performance.