This description of the structure of simulators suitable for use in the design of digital electronic systems includes the compiled code and event driven algorithms for digital electronic system simulators, together with timing verification as well as structural limitations and problems.

Your road map for meeting today's digital testing challenges Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge. There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as: * Binary Decision Diagrams (BDDs) and cycle-based simulation * Tester architectures/Standard Test Interface Language (STIL) * Practical algorithms written in a Hardware Design Language (HDL) * Fault tolerance * Behavioral Automatic Test Pattern Generation (ATPG) * The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

Analog Design Issues in Digital VLSI Circuits and Systems brings together in one place important contributions and up-to-date research results in this fast moving area. Analog Design Issues in Digital VLSI Circuits and Systems serves as an excellent reference, providing insight into some of the most challenging research issues in the field.

Mixed-Mode Simulation and Analog Multilevel Simulation addresses the problems of simulating entire mixed analog/digital systems in the time-domain. A complete hierarchy of modeling and simulation methods for analog and digital circuits is described. Mixed-Mode Simulation and Analog Multilevel Simulation also provides a chronology of the research in the field of mixed-mode simulation and analog multilevel simulation over the last ten to fifteen years. In addition, it provides enough information to the reader so that a prototype mixed-mode simulator could be developed using the algorithms in this book. Mixed-Mode Simulation and Analog Multilevel Simulation can also be used as documentation for the SPLICE family of mixed-mode programs as they are based on the algorithms and techniques described in this book.

Piecewise Linear (PL) approximation of non-linear behaviour is a well-known technique in synthesis and analysis of electrical networks. However, the PL description should be efficient in data storage and the description should allow simple retrieval of the stored information. Furthermore, it would be useful if the model description could handle a large class of piecewise linear mappings. Piecewise Linear Modeling and Analysis explains in detail all possible model descriptions for efficiently storing piecewise linear functions, starting with the Chua descriptions. Detailed explanation on how the model parameter can be obtained for a given mapping is provided and demonstrated by examples. The models are ranked to compare them and to show which model can handle the largest class of PL mappings. All model descriptions are implicitly related to the Linear Complementarity Problem and most solution techniques for this problem, like Katzenelson and Lemke, are discussed according to examples that are explained in detail. To analyse PL electrical networks a simulator is mandatory. Piecewise Linear Modeling and Analysis provides a detailed outline of a possible PL simulator, including pseudo-programming code. Several simulation domains like transient, AC and distortion are discussed. The book explains the attractive features of PL simulators with respect to mixed-level and mixed-signal simulation while paying due regard also to hierarchical simulation. Piecewise Linear Modeling and Analysis shows in detail how many existing components in electrical networks can be modeled. These range from digital logic and analog basic elements such as transistors to complex systems like Phase-Locked Loops and detection systems. Simulation results are also provided. The book concludes with a discussion on how to find multiple solutions for PL functions or networks. Again, the most common techniques are outlined using clear examples. Piecewise Linear Modeling and Analysis is an indispensable guide for researchers and designers interested in network theory, network synthesis and network analysis.