The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI technology. With gigahertz system clocks and ever accelerating design and process innovations, interconnects have become the limiting factor for both performance and density. This increasing impact of interconnects on the system implementation space necessitates new tools and analytic techniques to support the system designer. With respect to modeling and analysis, the response to interconnect dom inance is evolutionary. Atomistic- and grain-level models of interconnect structure, and performance models at multi-gigahertz operating frequencies, together guide the selection of improved materials and process technologies (e. g. , damascene copper wires, low-permittivity dielectrics). Previously in significant effects (e. g. , mutual inductance) are added into performance mod els, as older approximations (e. g. , lumped-capacitance gate load models) are discarded. However, at the system-level and chip planning level, the necessary response to interconnect dominance is revolutionary. Convergent design flows do not require only distributed RLC line models, repeater awareness, unifi cations with extraction and analysis, etc. Rather, issues such as wiring layer assignment, and early prediction of the resource and performance envelope for the system interconnect (in particular, based on statistical models of the system interconnect structure), also become critical. Indeed, system-level interconnect prediction has emerged as the enabler of improved interconnect modeling, more cost-effective system architectures, and more productive design technology.

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits. Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

"The SLIP workshop is a forum for the exchange of ideas at the interface between interconnect technology and physical design ... This year, in recognition of the highly diverse backgrounds and motivations of the attendees, SLIP 2001 has been organized around three mini-tutorials: a review of wire distribution models, a look under the hood of a variety of system level interconnect modeling programs, and back end of line yield modeling. These tutorials set the scene for the paper sessions that follow."--Forward.