Mathematics of Computing -- Parallelism.

Dr. Lenoski and Dr. Weber have experience with leading-edge research and practical issues involved in implementing large-scale parallel systems. They were key contributors to the architecture and design of the DASH multiprocessor. Currently, they are involved with commercializing scalable shared-memory technology.

Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.

Abstract: "This paper considers alternative directory protocols for providing cache coherence in shared-memory multiprocessors with 32 to 128 processors, where the state requirements of Dir[subscript N] may be considered too large. We consider Dir[subscript i]B, i = 1,2,4, Dir[subscript N], Tristate (also called superset), Coarse Vector, and three new protocols. The new protocols -- Gray-hardware, Gray-software, Home -- are optimizations of Tristate that use gray coding to favor near-neighbor sharing. Our results are the first to compare all these protocols with complete applications (and the first evaluation of Tristate with a non- synthetic workload). Results for three applications -- ocean (one dimensional sharing), appbt (three-dimensional sharing), and barnes (dynamic sharing) -- for 128 processors on the Wisconsin Wind Tunnel show that (a) Dir1B sends 15 to 43 times as many invalidation messages as Dir[subscript N], (b) Gray-software sends 1.0 to 4.7 times as many messages as Dir[subscript N], making it better than Tristate, Gray- Hardware, and Home, and (c) the choice between Dir[subscript i]B, Coarse Vector, and Gray-software depends on whether one wants to optimize for few sharers (Dir[subscript i]B), many sharers (Coarse Vector), or hedge one's bets between both alternatives (Gray-software)."

The book illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.

This book constitutes the refereed proceedings of the First International Symposium on Computer Science in Russia, CSR 2006. The 35 revised full theory papers and 29 revised application papers together with 3 invited talks address all major areas in computer science are addressed. The theory track deals with algorithms, protocols, data structures and more. The application part comprises programming and languages; computer architecture and hardware design among many more topics.