This book describes the concept and design of the capacitively-coupled chopper technique, which can be used in precision analog amplifiers. Readers will learn to design power-efficient amplifiers employing this technique, which can be powered by regular low supply voltage such as 2V and possibly having a +/-100V input common-mode voltage input. The authors provide both basic design concepts and detailed design examples, which cover the area of both operational and instrumentation amplifiers for multiple applications, particularly in power management and biomedical circuit designs.

To achieve low distortion, open-loop Class-D audio amplifiers require well designed power stages and expensive power supplies. Although the problem can be solved using feedback, for digital Class-D amplifiers, obtaining a effective design is difficult. The design of a 24-bit, 50W open-loop digital Class-D amplifier with 0.016% Total Harmonic Distortion plus Noise (THD+N), and 88% efficiency is presented and a novel discrete time feedback circuit is proposed. The feedback circuit monitors the effective duty ratio at the power stage output and adjusts the gate drive timing to counteract the effect of power stage non-idealities and supply noise. In-closed loop, a THD+N of 0.01% and distortion suppression up to 38dB have been achieved. The open-loop digital Class-D amplifier is implemented in two pans, the digital modulator fabricated in standard 0.35mum occupies 4000x4000mum 2, the power stage fabricated in high voltage 0.35mum CMOS occupies 2820x3444mum2. The feedback concept is verified using discrete components.

Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35mum HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.

Pulse Density Modulation- (PDM- ) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM- ) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO- ) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.