The 29th edition of the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2022) be held in person as a physical conference at the iconic Marina Bay Sands, Singapore from 18 21 July 2022 IPFA will continue to focus on the fundamental understanding of the electrical and physical characterization techniques and associated technologies that assist in probing the nature of wear out and failure in conventional and new CMOS devices, in turn resulting in improved knowhow of the physics of device circuit module failure that serves as critical input for future design for reliability We are also soliciting submissions in new and upcoming research areas including failure analysis for hardware security, reliability and failure analysis of power electronics, photovoltaic technologies, 2D Nanodevices and applications of machine learning and artificial intelligence to the field of failure analysis and reliability assessments

We are delighted to provide the proceedings of the sixth International Conference on Applied Engineering (ICAE), 2023, which was conducted in Batam on November 7th, 2023. This conference, which has as its theme "Synergizing Green Economy, Sustainable Development, and Digitalization for a Prosperous Future," is a significant international assembly that seeks to integrate technological innovation, economic expansion, and environmental sustainability. An ensemble of stakeholders, comprising policymakers, entrepreneurs, and experts, assembles to examine the mutually beneficial correlation that exists between digital advancements and a green economy. The acceptance rate for ICAE 2023 stands at 25%, leading to the selection of 28 substantial papers. The conference featured three distinct tracks: Informatics, Electronics, and Mechanicals. Two keynote addresses were delivered in conjunction with the outstanding technical paper presentations at the technical program. The keynote addresses were delivered by Dr. Ir. Basuki Rahmatul Alam, Chair of the IEEE EDS Indonesia Chapter and Senior Member of IEEE, and Dr. MK Radhakrishnan, Technical Consultant at NanoRel LLP in Singapore and Vice President of IEEE EDS. Coordination effectiveness with the steering committee was crucial to guaranteeing the conference's success. We wish to convey our profound gratitude for their consistent guidance and support that accompanied the entire undertaking. The ICAE Chair Committee deserves special recognition for their conscientiousness in finalizing the peer-review procedure of technical papers, which ultimately led to the creation of a technical program of exceptional quality. Furthermore, we would like to express our sincere appreciation to the Conference Managers and all the authors who submitted their papers for the ICAE 2023 conference for their invaluable assistance. Additionally, we appreciate the assistance of the EAI staff in facilitating the production of this publication.

Materials for Electronics Security and Assurance reviews the properties of materials that could enable devices that are resistant to tampering and manipulation. The book discusses recent advances in materials synthesis and characterization techniques for security applications. Topics addressed include anti-reverse engineering, detection, prevention, track and trace, fingerprinting, obfuscation, and how materials could enable these security solutions. The book introduces opportunities and challenges and provides a clear direction of the requirements for material-based solutions to address electronics security challenges. It is suitable for materials scientists and engineers who seek to enable future research directions, current computer and hardware security engineers who want to enable materials selection, and as a way to inspire cross-collaboration between both communities. - Discusses materials as enablers to provide electronics assurance, counterfeit detection/protection, and fingerprinting - Provides an overview of benefits and challenges of materials-based security solutions to inspire future materials research directions - Includes an introduction to material perspectives on hardware security to enable cross collaboration between materials, design, and testing

This is the first book dedicated to hands-on hardware security training. It includes a number of modules to demonstrate attacks on hardware devices and to assess the efficacy of the countermeasure techniques. This book aims to provide a holistic hands-on training to upper-level undergraduate engineering students, graduate students, security researchers, practitioners, and industry professionals, including design engineers, security engineers, system architects, and chief security officers. All the hands-on experiments presented in this book can be implemented on readily available Field Programmable Gate Array (FPGA) development boards, making it easy for academic and industry professionals to replicate the modules at low cost. This book enables readers to gain experiences on side-channel attacks, fault-injection attacks, optical probing attack, PUF, TRNGs, odometer, hardware Trojan insertion and detection, logic locking insertion and assessment, and more.

With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.