This book includes high-quality research papers presented at the Fourth International Conference on Communication, Computing and Electronics Systems (ICCCES 2022), held at the PPG Institute of Technology, Coimbatore, India, on September 15–16, 2022. The book focuses mainly on the research trends in cloud computing, mobile computing, artificial intelligence and advanced electronics systems. The topics covered are automation, VLSI, embedded systems, optical communication, RF communication, microwave engineering, artificial intelligence, deep learning, pattern recognition, communication networks, Internet of things, cyber-physical systems and healthcare informatics.

This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the various machine learning methods used in lithography, physical design, yield prediction, post-silicon performance analysis, reliability and failure analysis, power and thermal analysis, analog design, logic synthesis, verification, and neuromorphic design. Provides up-to-date information on machine learning in VLSI CAD for device modeling, layout verifications, yield prediction, post-silicon validation, and reliability; Discusses the use of machine learning techniques in the context of analog and digital synthesis; Demonstrates how to formulate VLSI CAD objectives as machine learning problems and provides a comprehensive treatment of their efficient solutions; Discusses the tradeoff between the cost of collecting data and prediction accuracy and provides a methodology for using prior data to reduce cost of data collection in the design, testing and validation of both analog and digital VLSI designs. From the Foreword As the semiconductor industry embraces the rising swell of cognitive systems and edge intelligence, this book could serve as a harbinger and example of the osmosis that will exist between our cognitive structures and methods, on the one hand, and the hardware architectures and technologies that will support them, on the other....As we transition from the computing era to the cognitive one, it behooves us to remember the success story of VLSI CAD and to earnestly seek the help of the invisible hand so that our future cognitive systems are used to design more powerful cognitive systems. This book is very much aligned with this on-going transition from computing to cognition, and it is with deep pleasure that I recommend it to all those who are actively engaged in this exciting transformation. Dr. Ruchir Puri, IBM Fellow, IBM Watson CTO & Chief Architect, IBM T. J. Watson Research Center

This book gathers outstanding research papers presented at the International Conference on Frontiers in Computing and Systems (COMSYS 2020), held on January 13–15, 2019 at Jalpaiguri Government Engineering College, West Bengal, India and jointly organized by the Department of Computer Science & Engineering and Department of Electronics & Communication Engineering. The book presents the latest research and results in various fields of machine learning, computational intelligence, VLSI, networks and systems, computational biology, and security, making it a rich source of reference material for academia and industry alike.

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the “trenches” of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

In a previous volume (ICT-Energy-Concepts Towards Zero-Power ICT; referenced below as Vol. 1), we addressed some of the fundamentals related to bridging the gap between the amount of energy required to operate portable/mobile ICT systems and the amount of energy available from ambient sources. The only viable solution appears to be to attack the gap from both sides, i.e. to reduce the amount of energy dissipated during computation and to improve the efficiency in energy-harvesting technologies. In this book, we build on those concepts and continue the discussion on energy efficiency and sustainability by addressing the minimisation of energy consumption at different levels across the ICT system stack, from hardware to software, as well as discussing energy consumption issues in high-performance computing (HPC), data centres and communication in sensor networks. This book was realised thanks to the contribution of the project ‘Coordinating Research Efforts of the ICT-Energy Community’ funded from the European Union under the Future and Emerging Technologies (FET) area of the Seventh Framework Programme for Research and Technological Development (grant agreement n. 611004).

This book constitutes the thoroughly refereed post-conference proceedings of the 19th and 20th International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2015 and 2016, held respectively in Hyderabad, India, on May 26, 2015 and in Chicago, IL, USA, on May 27, 2016. The 14 revised full papers presented (7 papers in 2015 and 7 papers in 2016) were carefully reviewed and selected from 28 submissions (14 in 2015 and 14 in 2016). The papers cover the following topics: parallel scheduling raising challenges multiple levels of abstractions; node level parallelism; minimization of energy consumption in task migration within a many-core chip; task replication in real-time scheduling context; data-driven approach to schedule GPU load; the use of lock-free data structures in OS scheduler; the influence between user behaviour (think time, more precisely) and parallel scheduling; Evalix, a predictor for job resource consumption; sophisticated and realistic simulation; space-filling curves leading to better scheduling of large-scale computers; discussion of real-life production experiences.

Neuromorphic engineering has just reached its 25th year as a discipline. In the first two decades neuromorphic engineers focused on building models of sensors, such as silicon cochleas and retinas, and building blocks such as silicon neurons and synapses. These designs have honed our skills in implementing sensors and neural networks in VLSI using analog and mixed mode circuits. Over the last decade the address event representation has been used to interface devices and computers from different designers and even different groups. This facility has been essential for our ability to combine sensors, neural networks, and actuators into neuromorphic systems. More recently, several big projects have emerged to build very large scale neuromorphic systems. The Telluride Neuromorphic Engineering Workshop (since 1994) and the CapoCaccia Cognitive Neuromorphic Engineering Workshop (since 2009) have been instrumental not only in creating a strongly connected research community, but also in introducing different groups to each other’s hardware. Many neuromorphic systems are first created at one of these workshops. With this special research topic, we showcase the state-of-the-art in neuromorphic systems.