Verifying Concurrent Processes Using Temporal Logic
Title | Verifying Concurrent Processes Using Temporal Logic PDF eBook |
Author | B. T. Hailpern |
Publisher | Springer Science & Business Media |
Pages | 220 |
Release | 1982-03 |
Genre | Computers |
ISBN | 9783540112051 |
Verifying Concurrent Processes Using Temporal Logic
Title | Verifying Concurrent Processes Using Temporal Logic PDF eBook |
Author | Brent Tzion Hailpern |
Publisher | |
Pages | 208 |
Release | 1982 |
Genre | Artificial intelligence |
ISBN | 9780387112053 |
Verifying Concurrent Processes Using Temporal Logic
Title | Verifying Concurrent Processes Using Temporal Logic PDF eBook |
Author | Brent Tzion Hailpern |
Publisher | |
Pages | 446 |
Release | 1980 |
Genre | Computer networks |
ISBN |
VERIFYING CONCURRENT PROCESSES USING TEMPORAL LOGIC
Title | VERIFYING CONCURRENT PROCESSES USING TEMPORAL LOGIC PDF eBook |
Author | Brent T. Hailpern |
Publisher | |
Pages | 208 |
Release | 1982 |
Genre | |
ISBN |
Temporal Verification of Reactive Systems
Title | Temporal Verification of Reactive Systems PDF eBook |
Author | Zohar Manna |
Publisher | Springer Science & Business Media |
Pages | 525 |
Release | 2012-12-06 |
Genre | Computers |
ISBN | 1461242223 |
This book is about the verification of reactive systems. A reactive system is a system that maintains an ongoing interaction with its environment, as opposed to computing some final value on termination. The family of reactive systems includes many classes of programs whose correct and reliable construction is con sidered to be particularly challenging, including concurrent programs, embedded and process control programs, and operating systems. Typical examples of such systems are an air traffic control system, programs controlling mechanical devices such as a train, or perpetually ongoing processes such as a nuclear reactor. With the expanding use of computers in safety-critical areas, where failure is potentially disastrous, correctness is crucial. This has led to the introduction of formal verification techniques, which give both users and designers of software and hardware systems greater confidence that the systems they build meet the desired specifications. Framework The approach promoted in this book is based on the use of temporal logic for specifying properties of reactive systems, and develops an extensive verification methodology for proving that a system meets its temporal specification. Reactive programs must be specified in terms of their ongoing behavior, and temporal logic provides an expressive and natural language for specifying this behavior. Our framework for specifying and verifying temporal properties of reactive systems is based on the following four components: 1. A computational model to describe the behavior of reactive systems. The model adopted in this book is that of a Fair Transition System (FTS).
Verifying Concurrent Prcesses [sic] Using Temporal Logic
Title | Verifying Concurrent Prcesses [sic] Using Temporal Logic PDF eBook |
Author | Brent Tzion Hailpern |
Publisher | |
Pages | |
Release | 1980 |
Genre | Computer programs |
ISBN |
Specification And Verification Of Systolic Arrays
Title | Specification And Verification Of Systolic Arrays PDF eBook |
Author | Magdy A Bayoumi |
Publisher | World Scientific |
Pages | 131 |
Release | 1999-08-05 |
Genre | Computers |
ISBN | 9814494992 |
Circuits and architectures have become more complex in terms of structure, interconnection topology, and data flow. Design correctness has become increasingly significant, as errors in design may result in strenuous debugging, or even in the repetition of a costly manufacturing process. Although circuit simulation has been used traditionally and widely as the technique for checking hardware and architectural designs, it does not guarantee the conformity of designs to specifications. Formal methods therefore become vital in guaranteeing the correctness of designs and have thus received a significant amount of attention in the CAD industry today.This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs.