Scientist and engineers as well as graduate students in the fields of This conference will be of interest to anyone involved in Physics, Electrical Engineering, Materials Science and Engineering, Reliability and Quality Management, both in industry and academia. One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in 3D IC integration. Stresses arising in 3D TSV interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration can lead to performance reduction, reliability-limiting degradation and failure of microelectronic products. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on the device characteristics must be understood and shared, and designers need a solution for managing stress. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in 3D IC integration. Modelling and simulation capabilities as well as materials characterization are demonstrated to evaluate the effect of stress on product performance.

Recent advances in semiconductor technology offer vertical interconnect access (via) that extend through silicon, popularly known as through silicon via (TSV). This book provides a comprehensive review of the theory behind TSVs while covering most recent advancements in materials, models and designs. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for Cu, carbon nanotube (CNT) and graphene nanoribbon (GNR) based TSVs are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR based TSVs are also discussed.

The latest advances in three-dimensional integrated circuit stacking technology With a focus on industrial applications, 3D IC Stacking Technology offers comprehensive coverage of design, test, and fabrication processing methods for three-dimensional device integration. Each chapter in this authoritative guide is written by industry experts and details a separate fabrication step. Future industry applications and cutting-edge design potential are also discussed. This is an essential resource for semiconductor engineers and portable device designers. 3D IC Stacking Technology covers: High density through silicon stacking (TSS) technology Practical design ecosystem for heterogeneous 3D IC products Design automation and TCAD tool solutions for through silicon via (TSV)-based 3D IC stack Process integration for TSV manufacturing High-aspect-ratio silicon etch for TSV Dielectric deposition for TSV Barrier and seed deposition Copper electrodeposition for TSV Chemical mechanical polishing for TSV applications Temporary and permanent bonding Assembly and test aspects of TSV technology

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology. Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.