This is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. The self-contained book covers all of the important digital circuit design styles found in modern CMOS chips, emphasizing solving design problems using the various logic styles available in CMOS.

本书介绍了模拟电路设计的基本概念, 说明了CMOS模拟集成电路设计技术的重要作用, 描述了MOS器件的物理模型及工作特性等.

The third edition of Hodges and Jackson’s Analysis and Design of Digital Integrated Circuits has been thoroughly revised and updated by a new co-author, Resve Saleh of the University of British Columbia. The new edition combines the approachability and concise nature of the Hodges and Jackson classic with a complete overhaul to bring the book into the 21st century. The new edition has replaced the emphasis on BiPolar with an emphasis on CMOS. The outdated MOS transistor model used throughout the book will be replaced with the now standard deep submicron model. The material on memory has been expanded and updated. As well the book now includes more on SPICE simulation and new problems that reflect recent technologies. The emphasis of the book is on design, but it does not neglect analysis and has as a goal to provide enough information so that a student can carry out analysis as well as be able to design a circuit. This book provides an excellent and balanced introduction to digital circuit design for both students and professionals.

This text and reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book.

When first published in 1996, this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated by Tony Chan Carusone, a University of Toronto colleague of Drs. Johns and Martin. Dr. Chan Carusone is a specialist in analog and digital IC design in communications and signal processing. This edition features extensive new material on CMOS IC device modeling, processing and layout. Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A/D converters. Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers.

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.