The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements. Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.

CMOS devices are scaled down and beyond pose significant process variability and reliability issues. Negative biased temperature instability (NBTI) and hot carrier injection (HCI) are well-known aging phenomena that degrade transistor and circuit performance. Yield analysis and optimization, which takes into account the manufacturing tolerances, model uncertainties, variations in the process parameters, and aging factors are known as indispensable components of the circuit design procedure. Process variability issues become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class F power amplifier was designed and evaluated using TSMC 0.18 [micrometer] RF technology. The PA’s output power and power-added efficiency were evaluated using the ADS simulation. Physical insight of transistor operation in the RF circuit environment was examined using the Sentaurus mixed-mode device and circuit simulation. The hot electron effect and device self-heating degraded the output power and power-added efficiency of the power amplifier, especially when both the input transistor and output transistor suffered high impact ionization rates and lattice heating.

Exciting new developments are enabling sensors to go beyond the realm of simple sensing of movement or capture of images to deliver information such as location in a built environment, the sense of touch, and the presence of chemicals. These sensors unlock the potential for smarter systems, allowing machines to interact with the world around them in more intelligent and sophisticated ways. Featuring contributions from authors working at the leading edge of sensor technology, Technologies for Smart Sensors and Sensor Fusion showcases the latest advancements in sensors with biotechnology, medical science, chemical detection, environmental monitoring, automotive, and industrial applications. This valuable reference describes the increasingly varied number of sensors that can be integrated into arrays, and examines the growing availability and computational power of communication devices that support the algorithms needed to reduce the raw sensor data from multiple sensors and convert it into the information needed by the sensor array to enable rapid transmission of the results to the required point. Using both SI and US units, the text: Provides a fundamental and analytical understanding of the underlying technology for smart sensors Discusses groundbreaking software and sensor systems as well as key issues surrounding sensor fusion Exemplifies the richness and diversity of development work in the world of smart sensors and sensor fusion Offering fresh insight into the sensors of the future, Technologies for Smart Sensors and Sensor Fusion not only exposes readers to trends but also inspires innovation in smart sensor and sensor system development.

Improving the performance of existing technologies has always been a focal practice in the development of computational systems. However, as circuitry is becoming more complex, conventional techniques are becoming outdated and new research methodologies are being implemented by designers. Performance Optimization Techniques in Analog, Mix-Signal, and Radio-Frequency Circuit Design features recent advances in the engineering of integrated systems with prominence placed on methods for maximizing the functionality of these systems. This book emphasizes prospective trends in the field and is an essential reference source for researchers, practitioners, engineers, and technology designers interested in emerging research and techniques in the performance optimization of different circuit designs.

With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.