This book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.

This book constitutes the refereed joint post-conference proceedings of the 6th International Symposium on High-Performance Computing, ISHPC 2005, held in, Japan, in 2005. It also includes the refereed post-proceedings of the First International Workshop on Advanced Low Power Systems 2006, ALPS2006, and some from the Workshop on Applications for PetaFLOPS Computing, APC 2005. A total of 42 papers were carefully selected from 76 submissions, covering a huge range of topics.

This book summarizes the landscape of cache replacement policies for CPU data caches. The emphasis is on algorithmic issues, so the authors start by defining a taxonomy that places previous policies into two broad categories, which they refer to as coarse-grained and fine-grained policies. Each of these categories is then divided into three subcategories that describe different approaches to solving the cache replacement problem, along with summaries of significant work in each category. Richer factors, including solutions that optimize for metrics beyond cache miss rates, that are tailored to multi-core settings, that consider interactions with prefetchers, and that consider new memory technologies, are then explored. The book concludes by discussing trends and challenges for future work. This book, which assumes that readers will have a basic understanding of computer architecture and caches, will be useful to academics and practitioners across the field.

This little book is conceived as a service to mathematicians attending the 1998 International Congress of Mathematicians in Berlin. It presents a comprehensive, condensed overview of mathematical activity in Berlin, from Leibniz almost to the present day (without, however, including biographies of living mathematicians). Since many towering figures in mathematical history worked in Berlin, most of the chapters of this book are concise biographies. These are held together by a few survey articles presenting the overall development of entire periods of scientific life at Berlin. Overlaps between various chapters and differences in style between the chap ters were inevitable, but sometimes this provided opportunities to show different aspects of a single historical event - for instance, the Kronecker-Weierstrass con troversy. The book aims at readability rather than scholarly completeness. There are no footnotes, only references to the individual bibliographies of each chapter. Still, we do hope that the texts brought together here, and written by the various authors for this volume, constitute a solid introduction to the history of Berlin mathematics.

This volume constitutes the papers of several workshops which were held in conjunction with the 38th International Conference on High Performance Computing, ISC High Performance 2023, held in Hamburg, Germany, during May 21–25, 2023. The 49 revised full papers presented in this book were carefully reviewed and selected from 70 submissions. ISC High Performance 2023 presents the following workshops: ​2nd International Workshop on Malleability Techniques Applications in High-Performance Computing (HPCMALL) 18th Workshop on Virtualization in High-Performance Cloud Computing (VHPC 23) HPC I/O in the Data Center (HPC IODC) Workshop on Converged Computing of Cloud, HPC, and Edge (WOCC’23) 7th International Workshop on In Situ Visualization (WOIV’23) Workshop on Monitoring and Operational Data Analytics (MODA23) 2nd Workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms: Scalable Infrastructures First International Workshop on RISC-V for HPC Second Combined Workshop on Interactive and Urgent Supercomputing (CWIUS) HPC on Heterogeneous Hardware (H3)