Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Digitally Assisted Pipeline ADCs: Theory and Implementation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction. Digitally Assisted Pipeline ADCs: Theory and Implementation describes in detail the implementation and measurement results of a 12-bit, 75-MSample/sec proof-of-concept prototype. The Experimental converter achieves power savings greater than 60% over conventional implementations. Digitally Assisted Pipeline ADCs: Theory and Implementation will be of interest to researchers and professionals interested in advances of state-of-the-art in A/D conversion techniques.

In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.

This book features a collection of high-quality, peer-reviewed papers presented at the Third International Conference on Intelligent Computing and Communication (ICICC 2019) held at the School of Engineering, Dayananda Sagar University, Bengaluru, India, on 7 – 8 June 2019. Discussing advanced and multi-disciplinary research regarding the design of smart computing and informatics, it focuses on innovation paradigms in system knowledge, intelligence and sustainability that can be applied to provide practical solutions to a number of problems in society, the environment and industry. Further, the book also addresses the deployment of emerging computational and knowledge transfer approaches, optimizing solutions in various disciplines of science, technology and healthcare.

This excellent reference proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. The book may also be used as a text for advanced reading on the subject.