The performance of the turn back switches and blocking switches are compared. This lead us to propose the "rotating switch" which combines the advantages of the turn back switch and the blocking switch; we then evaluate its performance relative to the blocking switch and the turn back switch."

Three approaches can be applied to determine the performance of parallel and distributed computer systems: measurement, simulation, and mathematical methods. This book introduces various network architectures for parallel and distributed systems as well as for systems-on-chips, and presents a strategy for developing a generator for automatic model derivation. It will appeal to researchers and students in network architecture design and performance analysis.

The International Workshop on "The Internet Challenge: Technology and Applications" is the fifth in a successful series of workshops that were established by Shanghai Jiao Tong University and Technische Universitat Berlin. The goal of those workshops is to bring together researchers from both universities in order to exchange research results achieved in common projects of the two partner universities or to present interesting new work that might lead to new cooperation. The series of workshops started in 1990 with the "International Workshop on Artificial Intelligence" and was continued with the "International Workshop on Advanced Software Technology" in 1994. Both workshops have been hosted by Shanghai Jiao Tong University. In 1998 the third workshop took place in Berlin. This "International Workshop on Communication Based Systems" was essentially based on results from the Graduiertenkolleg on Communication Based systems that was funded by the German Research Society (DFG) from 1991 to 2000. The fourth "International Workshop on Robotics and its Applications" was held in Shanghai in 2000 supported by VDIIVDE-GMA and GI.

Abstract: "In this correspondence, we propose a design and analysis technique for a class of Multistage Interconnection Networks (MINs). This class of MINs have finite buffers at the input side of their switch elements and operate in a synchronous packet-switched mode. We first examine the important issue of different clock periods in the synchronous MIN analysis. Then we analyze our 'small cycle' design with a simple analytical model and compare the results with that of a somewhat standard 'big cycle' model that is currently used. The significant performance improvement of our model is shown based on various clock width, data width, and buffer length."