This is an introduction to noise, describing fundamental noise sources and basic circuit analysis, discussing characterization of low-frequency noise and offering practical advice that bridges concepts of noise theory and modelling, characterization, CMOS technology and circuits. The text offers the latest research, reviewing the most recent publications and conference presentations. The book concludes with an introduction to noise in analog/RF circuits and describes how low-frequency noise can affect these circuits.

The main topic of this thesis is to investigate the CMOS scaling impacts on low-frequency noise properties. Such effects come from size (channel length/width) scaling, adoption of advanced doping profiles (halo pocket implantation), incorporation of alternative gate oxide (high-[Kappa]) and channel materials (SiGe). Device-level simulation capabilities have been developed to investigate low-frequency noise behavior. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation and a Hooge mobility fluctuation. Simulations based on such models have been conducted for high-[Kappa], SiGe and small gate area transistors, and the results have been correlated with experimental data, which reveals the important role of the CMOS scaling in the low-frequency noise behavior. In the study of high-[Kappa] gate dielectric it is found that carrier number fluctuation becomes the dominant noise source and the non-uniform trap energy distribution is critical to explain low frequency noise behavior. The negative impact of substrate halo doping on the low frequency noise is also studied quantitatively. Low frequency noise characteristics of Si/SiGe/Si hetero-channel MOSFETs (SiGe MOSFETs) are discussed; the study has been obtained in terms of the noise level dependence on gate bias, drain currents, and body bias, revealing the important role of the dual channels in the low-frequency noise behavior of Si/SiGe/Si hetero-channel devices. Low frequency noise characteristics in small gate area MOSFETs are studied in detail. Due to the ever decreasing gate area, the number of charge carriers in a MOSFET channel is continually going down, and single-electron low frequency noise phenomena (random telegraph noise, RTN) becomes visible, which is quite different from 1/f noise in standard MOSFETs. It is found that random telegraph noise is directly linked to Positive Bias Temperature Instability (PBTI): PBTI and RTN originate from the same physical process, charge trapping in the high-[Kappa] dielectric. The correlation between Id- and Ig-RTN is clearly observed. Ig-RTN is directly related to physical trapping or de-trapping and the Id-RTN reflects sensitivity to charge trapping as determined by gm. This dissertation has explored advanced TCAD simulations to overcome obstacles in low frequency noise and explained a comprehensive view and the underlying physics for low frequency noise in advanced CMOS technology.

This is an introduction to noise, describing fundamental noise sources and basic circuit analysis, discussing characterization of low-frequency noise and offering practical advice that bridges concepts of noise theory and modelling, characterization, CMOS technology and circuits. The text offers the latest research, reviewing the most recent publications and conference presentations. The book concludes with an introduction to noise in analog/RF circuits and describes how low-frequency noise can affect these circuits.

Low Power Circuit Design Using Advanced CMOS Technology is a summary of lectures from the first Advanced CMOS Technology Summer School (ACTS) 2017. The slides are selected from the handouts, while the text was edited according to the lecturers talk.ACTS is a joint activity supported by the IEEE Circuit and System Society (CASS) and the IEEE Solid-State Circuits Society (SSCS). The goal of the school is to provide society members as well researchers and engineers from industry the opportunity to learn about new emerging areas from leading experts in the field. ACTS is an example of high-level continuous education for junior engineers, teachers in academe, and students. ACTS was the results of a successful collaboration between societies, the local chapter leaders, and industry leaders. This summer school was the brainchild of Dr. Zhihua Wang, with strong support from volunteers from both the IEEE SSCS and CASS. In addition, the local companies, Synopsys China and Beijing IC Park, provided support.This first ACTS was held in the summer 2017 in Beijing. The lectures were given by academic researchers and industry experts, who presented each 6-hour long lectures on topics covering process technology, EDA skill, and circuit and layout design skills. The school was hosted and organized by the CASS Beijing Chapter, SSCS Beijing Chapter, and SSCS Tsinghua Student Chapter. The co-chairs of the first ACTS were Dr. Milin Zhang, Dr. Hanjun Jiang and Dr. Liyuan Liu. The first ACTS was a great success as illustrated by the many participants from all over China as well as by the publicity it has been received in various media outlets, including Xinhua News, one of the most popular news channels in China.

The chapter is intended to provide the reader with means to reduce low-frequency noise in Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET). It is demonstrated that low-resistivity source and drain electrodes can greatly lower the low-frequency noise level by suppressing their contribution to the total noise. Furthermore, new plasma processes having the advantages to work at low electron temperature can achieve a further reduction, thanks to the fabrication of a better gate oxide and to a reduction of damages generally induced by conventional plasma processes. Reducing the impact of the traps on the carrier flowing inside the channel by burying the channel can also achieve a reduction of the noise level, but unfortunately at the cost of a degradation of the electrical performances. Finally, the noise analysis of the low-frequency noise in accumulation-mode MOSFETs showed that these newly developed devices have a lower noise level than conventional structures, which, in addition to their superiority in term of electrical performances, establishes them as a serious platform for the next Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor (CMOS) technology.

Low Power Circuit Design Using Advanced CMOS Technology is a summary of lectures from the first Advanced CMOS Technology Summer School (ACTS) 2017. The slides are selected from the handouts, while the text was edited according to the lecturers talk.ACTS is a joint activity supported by the IEEE Circuit and System Society (CASS) and the IEEE Solid-State Circuits Society (SSCS). The goal of the school is to provide society members as well researchers and engineers from industry the opportunity to learn about new emerging areas from leading experts in the field. ACTS is an example of high-level continuous education for junior engineers, teachers in academe, and students. ACTS was the results of a successful collaboration between societies, the local chapter leaders, and industry leaders. This summer school was the brainchild of Dr. Zhihua Wang, with strong support from volunteers from both the IEEE SSCS and CASS. In addition, the local companies, Synopsys China and Beijing IC Park, provided support.This first ACTS was held in the summer 2017 in Beijing. The lectures were given by academic researchers and industry experts, who presented each 6-hour long lectures on topics covering process technology, EDA skill, and circuit and layout design skills. The school was hosted and organized by the CASS Beijing Chapter, SSCS Beijing Chapter, and SSCS Tsinghua Student Chapter. The co-chairs of the first ACTS were Dr. Milin Zhang, Dr. Hanjun Jiang and Dr. Liyuan Liu. The first ACTS was a great success as illustrated by the many participants from all over China as well as by the publicity it has been received in various media outlets, including Xinhua News, one of the most popular news channels in China.

Presented in this work is a novel design technique for a low-phase-noise high-frequency CMOS voltage-controlled oscillator. Phase noise is generated from electrical noise near DC, the oscillation frequency, and its harmonics. In CMOS technology, low-frequency flicker noise dominates the close-in phase noise of the VCO. The proposed technique minimizes the VCO phase noise by seeking to eliminate the effect of flicker noise on the phase n6se. This is accomplished by canceling out the DC component of the impulse sensitivity function (ISF) corresponding to each flicker-noise source, thus preventing the up-conversion of low-frequency noise into phase noise. The proposed circuit topology is a modified version of the complementary cross-coupled transconductance VCO, where additional feedback paths are introduced such that a designer can choose the feedback ratios, transistor sizes, and bias voltages to achieve the previously mentioned design objectives. A step-by-step design algorithm is presented along with a MATLAB script to aid in the computation of the ISFs and the phase noise of the VCO. Using this algorithm, a 5-GHz VCO was designed and fabricated in a 0.18m︡ CMOS process, and then tested for comparison with simulated results.