Photovoltaic (PV) modules undergo performance degradation depending on climatic conditions, applications, and system configurations. The performance degradation prediction of PV modules is primarily based on accelerated life testing (ALT) procedures. In order to further strengthen the ALT process, additional investigation of the power degradation of field aged PV modules in various configurations is required. A detailed investigation of 1,900 field aged (12-18 years) PV modules deployed in a power plant application was conducted for this study. Analysis was based on the current-voltage (I-V) measurement of all the 1,900 modules individually. I-V curve data of individual modules formed the basis for calculating the performance degradation of the modules. The percentage performance degradation and rates of degradation were compared to an earlier study done at the same plant. The current research was primarily focused on identifying the extent of potential induced degradation (PID) of individual modules with reference to the negative ground potential. To investigate this, the arrangement and connection of the individual modules/strings was examined in detail. The study also examined the extent of underperformance of every series string due to performance mismatch of individual modules in that string. The power loss due to individual module degradation and module mismatch at string level was then compared to the rated value.

Infant mortality rate of field deployed photovoltaic (PV) modules may be expected to be higher than that estimated by standard qualification tests. The reason for increased failure rates may be attributed to the high system voltages. High voltages (HV) in grid connected modules induce additional stress factors that cause new degradation mechanisms. These new degradation mechanisms are not recognized by qualification stress tests. To study and model the effect of high system voltages, recently, potential induced degradation (PID) test method has been introduced. Using PID studies, it has been reported that high voltage failure rates are essentially due to increased leakage currents from active semiconducting layer to the grounded module frame, through encapsulant and/or glass. This project involved designing and commissioning of a new PID test bed at Photovoltaic Reliability Laboratory (PRL) of Arizona State University (ASU) to study the mechanisms of HV induced degradation. In this study, PID stress tests have been performed on accelerated stress modules, in addition to fresh modules of crystalline silicon technology. Accelerated stressing includes thermal cycling (TC200 cycles) and damp heat (1000 hours) tests as per IEC 61215. Failure rates in field deployed modules that are exposed to long term weather conditions are better simulated by conducting HV tests on prior accelerated stress tested modules. The PID testing was performed in 3 phases on a set of 5 mono crystalline silicon modules. In Phase-I of PID test, a positive bias of +600 V was applied, between shorted leads and frame of each module, on 3 modules with conducting carbon coating on glass superstrate. The 3 module set was comprised of: 1 fresh control, TC200 and DH1000. The PID test was conducted in an environmental chamber by stressing the modules at 85°C, for 35 hours with an intermittent evaluation for Arrhenius effects. In the Phase-II, a negative bias of -600 V was applied on a set of 3 modules in the chamber as defined above. The 3 module set in phase-II was comprised of: control module from phase-I, TC200 and DH1000. In the Phase-III, the same set of 3 modules which were used in the phase-II again subjected to +600 V bias to observe the recovery of lost power during the Phase-II. Electrical performance, infrared (IR) and electroluminescence (EL) were done prior and post PID testing. It was observed that high voltage positive bias in the first phase resulted in little/no power loss, high voltage negative bias in the second phase caused significant power loss and the high voltage positive bias in the third phase resulted in major recovery of lost power.

Potential-induced degradation (PID) has received considerable attention in recent years due to its detrimental impact on photovoltaic (PV) module performance under field conditions. Both crystalline silicon (c-Si) and thin-film PV modules are susceptible to PID. While extensive studies have already been conducted in this area, the understanding of the PID phenomena is still incomplete and it remains a major problem in the PV industry. Herein, a critical review of the available literature is given to serve as a one-stop source for understanding the current status of PID research. This article also aims to provide an overview of future research paths to address PID-related issues. This paper consists of three parts. In the first part, the modelling of leakage current paths in the module package is discussed. The PID mechanisms in both c-Si and thin-film PV modules are also comprehensively reviewed. The second part summarizes various test methods to evaluate PV modules for PID. The last part focuses on studies related to PID in the omnipresent p-type c-Si PV modules. The dependence of temperature, humidity and voltage on the progression of PID is examined. Preventive measures against PID at the cell, module and system levels are illustrated. Moreover, PID recovery in standard p-type c-Si PV modules is also studied. Most of the findings from p-type c-Si PV modules are also applicable to other PV module technologies.

Potential induced degradation (PID) due to high system voltages is one of the major degradation mechanisms in photovoltaic (PV) modules, adversely affecting their performance due to the combined effects of the following factors: system voltage, superstrate/glass surface conductivity, encapsulant conductivity, silicon nitride anti-reflection coating property and interface property (glass/encapsulant; encapsulant/cell; encapsulant/backsheet). Previous studies carried out at ASU's Photovoltaic Reliability Laboratory (ASU-PRL) showed that only negative voltage bias (positive grounded systems) adversely affects the performance of commonly available crystalline silicon modules. In previous studies, the surface conductivity of the glass surface was obtained using either conductive carbon layer extending from the glass surface to the frame or humidity inside an environmental chamber. This thesis investigates the influence of glass surface conductivity disruption on PV modules. In this study, conductive carbon was applied only on the module's glass surface without extending to the frame and the surface conductivity was disrupted (no carbon layer) at 2cm distance from the periphery of frame inner edges. This study was carried out under dry heat at two different temperatures (60 °C and 85 °C) and three different negative bias voltages ( -300V, -400V, and -600V). To replicate closeness to the field conditions, half of the selected modules were pre-stressed under damp heat for 1000 hours (DH 1000) and the remaining half under 200 hours of thermal cycling (TC 200). When the surface continuity was disrupted by maintaining a 2 cm gap from the frame to the edge of the conductive layer, as demonstrated in this study, the degradation was found to be absent or negligibly small even after 35 hours of negative bias at elevated temperatures. This preliminary study appears to indicate that the modules could become immune to PID losses if the continuity of the glass surface conductivity is disrupted at the inside boundary of the frame. The surface conductivity of the glass, due to water layer formation in a humid condition, close to the frame could be disrupted just by applying a water repelling (hydrophobic) but high transmittance surface coating (such as teflon) or modifying the frame/glass edges with water repellent properties.

Over the past decade, degradation and power loss have been observed in PV modules resulting from the stress exerted by system voltage bias. This is due in part to qualification tests and standards that do not adequately evaluate for the durability of modules to the long-term effects of high voltage bias experienced in fielded arrays. High voltage can lead to module degradation by multiple mechanisms. The extent of the voltage bias degradation is linked to the leakage current or coulombs passed from the silicon active layer through the encapsulant and glass to the grounded module frame, which can be experimentally determined; however, competing processes make the effect non-linear and history-dependent. Appropriate testing methods and stress levels are described that demonstrate module durability to system voltage potential-induced degradation (PID) mechanisms. This information, along with outdoor testing that is in progress, is used to estimate the acceleration factors needed to evaluate the durability of modules to system voltage stress. Na-rich precipitates are observed on the cell surface after stressing the module to induce PID in damp heat with negative bias applied to the active layer.

Since the generation of solar energy is increasing and getting important worldwide .PV systems is becoming bigger with increasing the amount of serially interconnected panels. These panels are exposed to high potential relative to the ground which causing high voltage stresses (HVS). This HVS causing instability of the solar panels depending on some factors which cause an unwanted property called potential induced degradation (PID). The factors which effect on the PID are (Voltage, humidity and high temp) which generate leakage current between the solar cells and the ground. The key is to understand the PID phenomenon and the leakage current property which still not understandable.