The SiGe BiCMOS technology is the cost-effective solution for high-speed communications applications due to its RF/analog properties and CMOS compatibility. The main challenge with the optimization of SiGe HBT is to achieve both high speed and high breakdown performance simultaneously. This thesis investigates the optimization of the collector profile to attain multiple variants of SiGe HBTs, namely high speed, standard and high voltage devices, in one BiCMOS technology. Using process and device simulations, the device performance is enhanced by base and collector profile optimization to minimize base transit time and collector delay. Variants of SiGe HBTs with multiple cutoff frequencies and breakdown voltages are achieved by proper choice of collector doping concentration using selectively-implanted collectors (SIC). Three SiGe npn transistors with fT/BVCEO values of 80GHz/2V, 60GHz/2.9V and 40GHz/4.8V are successfully fabricated in standard 0.18 mum CMOS technology by an industrial foundry, with minimal extra process complexity.

This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.