This book constitutes the refereed proceedings of the Third International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2006, held in Yokohama, Japan in October 2006. The 12 revised papers of FDTC 2006 are presented together with nine papers from FDTC 2004 and FDTC 2005 that passed a second round of reviewing. They all provide a comprehensive introduction to the issues faced by designers of robust cryptographic devices.

This book consolidates several key aspects from the state-of-the-art research in symmetric key cryptography, which is among the cornerstones of digital security. It presents the content in an informative yet beginner-friendly, accompanied with toy examples and comprehensible graphics. In particular, it highlights the recent developments in tool-assisted analysis of ciphers. Furthermore, promising device-dependent attacks, such as fault attack and side channel attacks on symmetric key ciphers, are discussed in detail. One salient feature of this book is to present a detailed analysis of various fault countermeasures. The coverage of our book is quite diverse—it ranges from prerequisite information, latest research contribution as well as future research directions. It caters to students and researchers working in the field of cryptography.

In this book, a number of innovative fault diagnosis algorithms in recently years are introduced. These methods can detect failures of various types of system effectively, and with a relatively high significance.

This book presents a collection of automated methods that are useful for different aspects of fault analysis in cryptography. The first part focuses on automated analysis of symmetric cipher design specifications, software implementations, and hardware circuits. The second part provides automated deployment of countermeasures. The third part provides automated evaluation of countermeasures against fault attacks. Finally, the fourth part focuses on automating fault attack experiments. The presented methods enable software developers, circuit designers, and cryptographers to test and harden their products.

This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.

In the 1970s researchers noticed that radioactive particles produced by elements naturally present in packaging material could cause bits to flip in sensitive areas of electronic chips. Research into the effect of cosmic rays on semiconductors, an area of particular interest in the aerospace industry, led to methods of hardening electronic devices designed for harsh environments. Ultimately various mechanisms for fault creation and propagation were discovered, and in particular it was noted that many cryptographic algorithms succumb to so-called fault attacks. Preventing fault attacks without sacrificing performance is nontrivial and this is the subject of this book. Part I deals with side-channel analysis and its relevance to fault attacks. The chapters in Part II cover fault analysis in secret key cryptography, with chapters on block ciphers, fault analysis of DES and AES, countermeasures for symmetric-key ciphers, and countermeasures against attacks on AES. Part III deals with fault analysis in public key cryptography, with chapters dedicated to classical RSA and RSA-CRT implementations, elliptic curve cryptosystems and countermeasures using fault detection, devices resilient to fault injection attacks, lattice-based fault attacks on signatures, and fault attacks on pairing-based cryptography. Part IV examines fault attacks on stream ciphers and how faults interact with countermeasures used to prevent power analysis attacks. Finally, Part V contains chapters that explain how fault attacks are implemented, with chapters on fault injection technologies for microprocessors, and fault injection and key retrieval experiments on a widely used evaluation board. This is the first book on this topic and will be of interest to researchers and practitioners engaged with cryptographic engineering.

This book constitutes the refereed proceedings of the 10th Interntaional Workshop on Cryptographic Hardware and Embedded Systems, CHES 2008, held in Washington, D.C., USA, during August 10-13, 2008. The book contains 2 invited talks and 27 revised full papers which were carefully reviewed and selected from 107 submissions. The papers are organized in topical sections on side channel analysis, implementations, fault analysis, random number generation, and cryptography and cryptanalysis.