In recent years, the abundant advantages of quantum physics, quantum dots, quantum wires, quantum wells, and nanocrystals in various applications have attracted considerable scientific attention in the field of nonvolatile memory (NVM). Nanocrystals are the driving elements that have helped nonvolatile flash memory technology reach its distinguished height, but new approaches are still needed to strengthen nanocrystal-based nonvolatile technology for future applications. This book presents comprehensive knowledge on nanocrystal fabrication methods and applications of nanocrystals in baseline NVM and emerging NVM technologies and the chapters are written by experts in the field from all over the globe. The book presents a detailed analysis on nanocrystal-based emerging devices by a high-level researcher in the field. It has a unique chapter especially dedicated to graphene-based flash memory devices, considering the importance of carbon allotropes in future applications. This updated edition covers emerging ferroelectric memory device, which is a technology for the future, and the chapter is contributed by the well-known Ferroelectric Memory Company, Germany. It includes information related to the applications of emerging memories in sensors and the chapter is contributed by Ajou University, South Korea. The book introduces a new chapter for emerging NVM technology in artificial intelligence and the chapter is contributed by University College London, UK. It guides the readers throughout with appropriate illustrations, excellent figures, and references in each chapter. It is a valuable tool for researchers and developers from the fields of electronics, semiconductors, nanotechnology, materials science, and solid-state memories.

In recent years, utilization of the abundant advantages of quantum physics, quantum dots, quantum wires, quantum wells, and nanocrystals has attracted considerable scientific attention in the field of nonvolatile memory. Nanocrystals are the driving element that have brought the nonvolatile flash memory technology to a distinguished height. However, new approaches are still required to strengthen this technology for future applications. This book details the methods of fabrication of nanocrystals and their application in baseline nonvolatile memory and emerging nonvolatile memory technologies. The chapters have been written by renowned experts of the field and will provide an in-depth understanding of these technologies. The book is a valuable tool for research and development sectors associated with electronics, semiconductors, nanotechnology, material sciences, solid state memories, and electronic devices.

Many recent studies have been conducted on optically transparent and mechanically flexible polymer memory devices due to its additional benefits in comparison to conventional electronic devices for various applications, such as vision-free products, see-through electronic devices; head-up displays, and produces a class of system-on-glass for use in see through and flexible electronic devices. There are numerous studies on transparent and flexible non-volatile memory (NVM) based on organic thin film transistor (OTFT) using different charge trap mediums. Although some promising results have been achieved in OTFT study, however, the fabrication process is complicated with many stacking layers to achieve the bistable memory effect with three-terminal contacts to operate the transistors. Therefore, for simplicity and ease in fabrication while achieving the bistable memory effect, the transparent and flexible organic bistable device (OBD) has been designed as metal-insulator-semiconductor (MIS) structure with two-terminal contacts to operate the device and using metal nanoparticles as charge trap medium has been of interest lately. The advantages of metallic nanoparticles storage layers stem from the large work functions difference with Si substrate, which ensures deep potential wells that enhance carrier confinement; hence avoiding retention loss. In addition, noble metals such as gold do not oxidize and do not react with the surrounding dielectric layers. Hence, a simple fabrication route using a simple solution process to construct a large area, optically transparent and flexible memory based on MIS structure with embedded AuNPs is proposed in this study. The preliminary study has begun with the fabrication of opaque and rigid MIS memory devices using p-type Si substrate. The organic-inorganic (hybrid) dielectric polymethylsilsesquioxane (PMSSQ) embedded with gold nanoparticles (AuNPs) are used as the insulator layer and charge storage medium in the MIS structure. The use of polymer materials as insulator layer is driven by the possibility of enabling new applications in flexible and transparent electronic devices. Polymer materials offer an alternative fabrication process for the large area electronics, because it provides simpler process, lower cost, and higher throughput, compared with the vacuumdeposition- based process. In this preliminary study, spin-coating method is used to deposit the PMSSQ and AuNPs in polymer host. Subsequently, the electrical characterization has been performed on a MIS NVM device to understand the transport mechanisms through thin insulator and proposed. Although some promising memory characteristics have been obtained from preliminary study; however, spin-coating deposition of AuNPs in the polymer host results in high percentage of non-operational non-volatile memory devices due to the non-uniformly distributed AuNPs attributed to the centrifugal force during spin-coating. Therefore, a novel hydrothermally grown AuNPs directly on the Si substrate has been proposed to improve the distribution of AuNPs. Then, the research proceeds to realize transparent and flexible NVM devices using a simple solution process. Here, the MIS stacking structure is constructed on the flexible indium-tin-oxide (ITO) coated polyethylene terephthalate (PET) as a bottom transparent and conducting electrode, and the replacement of p-Si substrate with pentacene as an active layer. However, they also suffer non-uniformity in AuNPs due to spin-coating of PMSSQ. Lastly in an attempt to achieve non-volatile memory devices based on simple metal-insulatormetal (MIM) structure, AuNPs embedded in parylene-C with two sandwiching metals were realized. Electrical characterization has been performed on these MIM devices to examine and propose the charge transport mechanisms. As a result, it has better yield of operational nonvolatile memory devices because the vapor deposition of parylene does not disturbed the AuNPs. Further the parylene deposition does not introduce thermal stress on the flexible ITO coated PET substrate.

"Non-volatile memory (NVM) technology is widely used for data storage applications and embedded systems. Flash memory has been the most popular kind of NVM owing to the high demand of portable electronic devices in the market. One way to implement NVM is by incorporating a floating gate in the device structure [...]. Nanodot based memory devices have gained a lot of importance recently due to their potential in overcoming the limitations of conventional conductive floating gate based memory devices. The presence of nanodots in the floating gate can provide the additional advantage of discrete storage of charge and overcome the limitations of the conventional NVM devices by allowing further scaling of the tunnel oxide. Each insulated nanocrystalline dot can trap and de-trap charges based on the applied gate voltage and hence cause a shift in the threshold voltage. Distributed storage of charge prevents the device from being vulnerable to fatal leakage owing to a single leakage path, enhancing its non-volatility and retention characteristics. Since the means of charge storage is now discrete, the devices are immune to stress induced leakage current [...]. This work proposes the study and comparison of fabrication techniques of Nickel nanodots (Ni-NDs). The project will thus contribute to a better understanding of nanostructure formation, in particular, comparing equilibrium and non-equilibrium processing environments. In order to prove the applicability of Ni-NDs for memory devices, some of the Ni-NDs structures produced will be implemented in a sandwich configuration to verify storage of electrical charges. In this sandwich configuration the Ni-NDs are in between two layers of SiO2 which act as the control and tunnel oxide, respectively. The target size of the Ni-NDs is on the order of a few tens of nanometers. Although it is important to reduce the size of the nanodots considerably, it is equally important to integrate an adequate number of dots under the gate. The advantages that a nanostructured floating gate offers over the conventional floating gate can only be exploited if the nanodots obtained are within 10 nm [...]. Different approaches to Ni-NDs formation are investigated, namely, using plasma-based processes and thermal annealing. The tunnel and control oxides will be deposited by plasma sputtering and/or thermal growth. Variable angle spectroscopic ellipsometry (VASE) will be used to measure the thickness of the Ni/SiO2 films and atomic force microscopy (AFM) to characterize the topography after the Ni-NDs formation. Aluminum contacts will be produced for conducting hysteresis loop measurements, followed by generation of capacitance-voltage (C-V) curves."--Chapter 1.