This book talks about the Specification and Verification of Distributed Shared Memory Relaxed Consistency Models specifically Weak Consistency Models. For this, an abstract Distributed Shared Memory (DSM) has been designed and implemented using CADP (Construction and Analysis of Distributed Processes). In DSM, sequential consistency unnecessarily reduces the performance of the system because it does not allow reordering or pipelining the memory operations. Weak consistency allows the reordering of memory events and buffering or pipelining of memory accesses so weak consistency improves the performance of the DSM system. For any critical system, it is very important to develop methods that increase our confidence in the correctness of such systems. One such method for the correctness of critical systems is formal verification. For verification of the weak consistency model, the properties of weak consistency have been specified and verified on the Abstract DSM System using CADP Toolbox.

The shared memory systems should support parallelization at the computation (multiprocessor), communication (Network-on-Chip, NoC) and memory architecture levels to exploit the potential performance benefits. Such systems are facing the critical issues of memory consistency and coherence. Memory consistency issue arises due to the unconstrained operations which sometimes lead to the unexpected behavior of the systems. Memory consistency models are used to resolve this issue. Relaxed or weaker consistency models enforce less ordering constraints on the memory operations and exploit system optimizations compared to the stricter models. This book discusses the novel realization schemes and scalability analysis of strict Sequential Consistency (SC) model and relaxed memory consistency models: Total Store Ordering (TSO), Partial Store Ordering (PSO), Weak Ordering (WO), Release Consistency (RC), and Protected Release Consistency (PRC) in the NoC based distributed shared memory multiprocessor systems. This study should help the average readers and professionals to understand the critical issue of memory consistency both in the NoC based systems and general purpose multiprocessor systems.

Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

Distributed Shared Memory (DSM) is a collection of nodes or clusters, each with its own memory connected by an interconnected network. The key issue in DSM is keeping the memory pages consistent. It refers to the degree of consistency that has to be maintained for the shared memory data. Maintaining perfect consistency is especially painful when the difference between the latency and/or throughput of memory accesses on the one hand, and the network connecting the machines on which these copies reside on the other, is big. The solution might be to accept less than perfect consistency as the price for better performance. This paper reviews various memory consistency models which are used in different DSM systems.

This work investigates the feasibility of data consistency models to be used in Distributed Shared Memory (DSM) for Wireless Sensor Networks (WSN) to enable more powerful distributed systems with reliable data exchange. It starts with an introduction of WSN and consistency related approaches. Based on these basics, mechanisms that enable data consistency are discussed as a theoretical framework for the prototypical implementation of a data consistency providing middleware that was implemented as part of this work. The proposed middleware adapts the mechanisms known from the original memory consistency approaches to make them usable in the sensor network area and also proposes own low cost mechanisms. The latter are at least partially based on the idea that within the shared memory in WSNs the information is the major concern and by that the replica update rates can be tailored to the application. In order to allow for ease of use of the middleware, the replication schemes and the consistency mechanisms are defined by the application engineer as a policy. The most appropriate memory consistency models were implemented and evaluated using the framework proposed in this work.

The papers present in this text survey both distributed shared memory (DSM) efforts and commercial DSM systems. The book discusses relevant issues that make the concept of DSM one of the most attractive approaches for building large-scale, high-performance multiprocessor systems. The authors provide a general introduction to the DSM field as well as a broad survey of the basic DSM concepts, mechanisms, design issues, and systems. The book concentrates on basic DSM algorithms, their enhancements, and their performance evaluation. In addition, it details implementations that employ DSM solutions at the software and the hardware level. This guide is a research and development reference that provides state-of-the art information that will be useful to architects, designers, and programmers of DSM systems.