Understanding and emulating human-like intelligence has been a long-standing goal of researchers in various domains leading to the emergence of an inter-disciplinary area called Brain-inspired or Neuromorphic Computing. This research area aims to achieve brain- like intelligence and energy efficiency by understanding and emulating its functionality. In the contemporary world of big data-driven analytics that has fueled ever-increasing demands for computing power, combined with the end of Moore's law scaling, the sheer energy cost of providing exascale-compute capability could soon make it economically and ecologically unsustainable. It, therefore, becomes imperative to explore alternate and more energy-efficient computing paradigms and the human brain, with its 20 W operating power budget, provides the ideal inspiration for building these future computing systems. Spiking Neural Networks (SNNs) are a class of biologically-inspired algorithms designed to mimic natural neural networks found in the brain. Besides playing an important role in biological simulations for neuroscience-related studies, SNNs are recently gaining traction as low- power counterparts of high-precision DNNs. However, in order to build systems with brain-like energy efficiency, we need to capture the functionality of billions of neurons and their communication mechanism in hardware, and this requires innovations at the device/circuit, architecture, algorithm and application levels of the computing stack. Further, efficiently utilizing and incorporating the SNN-led temporal computing paradigm in day-to-day tasks on time-dependent data also requires considerable algorithmic and architectural innovations. With these over-arching princi- ples, this dissertation is aimed at addressing the following architectural and algorithmic issues in SNN inference and training: (i) Investigating the design space of scalable, low- power SNNs by taking a holistic approach spanning the device/circuit levels for designing extremely low power spiking neurons and synapses, architectural solutions for efficient scal- ing of these networks, as well as algorithm-level optimizations for improving the accuracy of SNN models. Further, the SNN characteristics are compared against those of deep/analog neural networks (DNN/ANN), the de-facto drivers of modern AI. Based on this study, a low-power SNN, ANN and hybrid SNN-ANN inference architecture is designed using spintronics-based Magnetic Tunnel Junction (MTJ) devices, while also accounting for the deep interactions between the algorithm and the device. (ii) Training an SNN to solve a problem in a user-level application has so far proved to be challenging due to its discrete and temporal nature. SNNs are, therefore, often converted from high-precision ANNs that can be easily trained using gradient descent-based backpropagation. In this chapter, we study the effectiveness of existing ANN-SNN conversion techniques on sparse event-based data emitted by a neuromorphic camera -- several low-power, hardware-friendly techniques are proposed to boost conversion accuracy and their efficacy is evaluated on a gesture recognition task. (iii) Next, we address the computational challenges involved in train- ing a deep SNN using gradient-descent backpropagation, which is the most effective and scalable technique for training DNNs and SNNs from scratch. By reducing the memory footprint and computational overhead of backpropagation through time-based SNN train- ing, we enable the training and exploration of deeper SNNs on resource-limited hardware platforms including edge devices. Techniques such as re-computation, approximation and a combination thereof, are explored in the context of SNN training. In a nutshell, this dissertation identifies the major compute and memory bottlenecks afflicting SNNs today and proposes efficient algorithm-architecture co-design techniques to alleviate them, with the ultimate goal of facilitating the adaption of energy-efficient Neuromorphic Computing in the mainstream computing paradigm.

High-Performance Computing using FPGA covers the area of high performance reconfigurable computing (HPRC). This book provides an overview of architectures, tools and applications for High-Performance Reconfigurable Computing (HPRC). FPGAs offer very high I/O bandwidth and fine-grained, custom and flexible parallelism and with the ever-increasing computational needs coupled with the frequency/power wall, the increasing maturity and capabilities of FPGAs, and the advent of multicore processors which has caused the acceptance of parallel computational models. The Part on architectures will introduce different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHREC’s Novo-G and EPCC’s Maxwell systems; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFL’s CONFETTI system. The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on C-to-Gate tools (such as Impulse-C, AutoESL, Handel-C, MORA-C++); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsoft’s Kiwi and Alchemy projects). The part on Applications will present case from several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling.

If engineering is the art and science of technical problem solving, systems architecting happens when you don't yet know what the problem is. The third edition of a highly respected bestseller, The Art of Systems Architecting provides in-depth coverage of the least understood part of systems design: moving from a vague concept and limited resources

A gentle introduction to genetic algorithms. Genetic algorithms revisited: mathematical foundations. Computer implementation of a genetic algorithm. Some applications of genetic algorithms. Advanced operators and techniques in genetic search. Introduction to genetics-based machine learning. Applications of genetics-based machine learning. A look back, a glance ahead. A review of combinatorics and elementary probability. Pascal with random number generation for fortran, basic, and cobol programmers. A simple genetic algorithm (SGA) in pascal. A simple classifier system(SCS) in pascal. Partition coefficient transforms for problem-coding analysis.

The primary purpose of this book is to capture the state-of-the-art in Cloud Computing technologies and applications. The book will also aim to identify potential research directions and technologies that will facilitate creation a global market-place of cloud computing services supporting scientific, industrial, business, and consumer applications. We expect the book to serve as a reference for larger audience such as systems architects, practitioners, developers, new researchers and graduate level students. This area of research is relatively recent, and as such has no existing reference book that addresses it. This book will be a timely contribution to a field that is gaining considerable research interest, momentum, and is expected to be of increasing interest to commercial developers. The book is targeted for professional computer science developers and graduate students especially at Masters level. As Cloud Computing is recognized as one of the top five emerging technologies that will have a major impact on the quality of science and society over the next 20 years, its knowledge will help position our readers at the forefront of the field.

Until the late 1980s, information processing was associated with large mainframe computers and huge tape drives. During the 1990s, this trend shifted toward information processing with personal computers, or PCs. The trend toward miniaturization continues and in the future the majority of information processing systems will be small mobile computers, many of which will be embedded into larger products and interfaced to the physical environment. Hence, these kinds of systems are called embedded systems. Embedded systems together with their physical environment are called cyber-physical systems. Examples include systems such as transportation and fabrication equipment. It is expected that the total market volume of embedded systems will be significantly larger than that of traditional information processing systems such as PCs and mainframes. Embedded systems share a number of common characteristics. For example, they must be dependable, efficient, meet real-time constraints and require customized user interfaces (instead of generic keyboard and mouse interfaces). Therefore, it makes sense to consider common principles of embedded system design. Embedded System Design starts with an introduction into the area and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, like real-time operating systems. The book also discusses evaluation and validation techniques for embedded systems. Furthermore, the book presents an overview of techniques for mapping applications to execution platforms. Due to the importance of resource efficiency, the book also contains a selected set of optimization techniques for embedded systems, including special compilation techniques. The book closes with a brief survey on testing. Embedded System Design can be used as a text book for courses on embedded systems and as a source which provides pointers to relevant material in the area for PhD students and teachers. It assumes a basic knowledge of information processing hardware and software. Courseware related to this book is available at http://ls12-www.cs.tu-dortmund.de/~marwedel.

RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM’s potential novel applications beyond the NVM applications.