CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cutoff frequencies of about 50 GHz have been reported for 0.18 æm CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of today's popular wireless products, such as cell phones, GPS (Global Positioning System) and Bluetooth. Of course, the great interest in RF CMOS comes from the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. This book discusses many of the challenges facing the CMOS RF circuit designer in terms of device modeling and characterization, which are crucial issues in circuit simulation and design.

MOSFET radio-frequency characterization and modeling is studied, both with SOI CMOS and bulk CMOS technologies. The network analyzer measurement uncertainties are studied, as is their effect on the small signal parameter extraction of MOS devices. These results can be used as guidelines for designing MOS RF characterization layouts with as small an AC extraction error as possible. The results can also be used in RF model extraction as criteria for required optimization accuracy. Modifications to the digital CMOS model equivalent circuit are studied to achieve better RF behavior for the MOS model. The benefit of absorbing the drain and source parasitic series resistances into the current description is evaluated. It seems that correct high-frequency behavior is not possible to describe using this technique. The series resistances need to be defined extrinsically. Different bulk network alternatives were evaluated using scalable device models up to 10 GHz. Accurate output impedance behavior of the model requires a bulk resistance network. It seems that good accuracy improvement is achieved with just a single bulk resistor. Additional improvement is achieved by increasing the number of resistors to three. At this used frequency range no further accuracy improvement was achieved by increasing the resistor amount over three. Two modeling approaches describing the distributed gate behavior are also studied with different MOS transistor layouts. Both approaches improve the RF characteristics to some extent but with limited device geometry. Both distributed gate models describe well the high frequency device behavior of devices not commonly used at radio frequencies.

At the 90-nm node, silicon technologies have reached a point where the transistor fT and f MAX simultaneously exceed 150 GHz, with a 1.2 V supply. With low fabrication costs for high volumes of circuits, RF-CMOS technologies are ideally suited to realize exciting new high bandwidth consumer products that operate in the mm-wave regime. Before this can happen, models of both active and passive devices will require a high degree of accuracy from DC, all the way up to mm-wave frequencies. This thesis presents new techniques that help leverage the power of measurements to characterize and model devices of nano-CMOS technologies well into the mm-wave regime. In particular, two new de-embedding techniques are devised in order to improve measurement accuracy, and reduce wafer area consumption. Moreover, the measured characteristics of various microstrip lines, varactors, and n-MOSFETs fabricated in a 90-nm RF-CMOS technology are analyzed in order to identify optimal geometries for high frequency design. An extraction methodology for a scalable physical model of accumulation-mode MOS varactors is also included.

Lastly, the design strategies of a low noise amplifier based on the developed noise models and extracted noise information are presented as a guide line to choose the device size and bias condition of the transistors. The impact of the model accuracy on the simulated noise performance of a two-stage low noise amplifier is also presented.