Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs. Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field Provides complete coverage of rewiring from an introductory to intermediate level Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples Readers can directly apply the described techniques to real-world VLSI design issues Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.

Demonstrates techniques which will allow rewiring rates ofover 95%, enabling adoption of deep sub-micron chips for industrialapplications Logic synthesis is an essential part of the modern digital ICdesign process in semi-conductor industry. This book discusses alogic synthesis technique called “rewiring” and itslatest technical advancement in term of rewirability. Rewiringtechnique has surfaced in academic research since 1993 and there iscurrently no book available on the market which systematically andcomprehensively discusses this rewiring technology. The authorscover logic transformation techniques with concentration onrewiring. For many decades, the effect of wiring on logicstructures has been ignored due to an ideal view of wires and theirnegligible role in the circuit performance. However intoday’s semiconductor technology wiring is the major playerin circuit performance degeneration and logic synthesis engines canbe improved to deal with this through wire-based transformations.This book introduces the automatic test pattern generation(ATPG)-based rewiring techniques, which are recently active in therealm of logic synthesis/verification of VLSI/SOC designs. Unique comprehensive coverage of semiconductor rewiringtechniques written by leading researchers in the field Provides complete coverage of rewiring from an introductory tointermediate level Rewiring is explained as a flexible technique for Boolean logicsynthesis, introducing the concept of Boolean circuittransformation and testing, with examples Readers can directly apply the described techniques toreal-world VLSI design issues Focuses on the automatic test pattern generation (ATPG) basedrewiring methods although some non-ATPG based rewiring methods suchas graph based alternative wiring (GBAW), and “set of pairsof functions to be distinguished” (SPFD) based rewiring arealso discussed A valuable resource for researchers and postgraduate students inVLSI and SoC design, as well as digital design engineers, EDAsoftware developers, and design automation experts that specializein the synthesis and optimization of logical circuits.

Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.

The three-volume proceedings LNCS 12491, 12492, and 12493 constitutes the proceedings of the 26th International Conference on the Theory and Application of Cryptology and Information Security, ASIACRYPT 2020, which was held during December 7-11, 2020. The conference was planned to take place in Daejeon, South Korea, but changed to an online format due to the COVID-19 pandemic. The total of 85 full papers presented in these proceedings was carefully reviewed and selected from 316 submissions. The papers were organized in topical sections as follows: Part I: Best paper awards; encryption schemes.- post-quantum cryptography; cryptanalysis; symmetric key cryptography; message authentication codes; side-channel analysis. Part II: public key cryptography; lattice-based cryptography; isogeny-based cryptography; quantum algorithms; authenticated key exchange. Part III: multi-party computation; secret sharing; attribute-based encryption; updatable encryption; zero knowledge; blockchains and contact tracing.