Low availability, high cost, and poor performance of radiation hardened (rad-hard) equipment has driven the market to rely on commercial-off- the-shelf (COTS) equipment for the computing needs of today's spacecraft. This thesis describes the tailoring of a COTS embedded real-time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation- induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware design used for this research is an acceptable fault-tolerant design candidate for the main processor for space-based applications. We found that a COTS embedded real-time operating system could be tailored to support the TMR hardware. The HCI accepts serial data from the TMR, correctly identifies the source of the error, allows for processor mode selection and provides system- and board-level reset capabilities. The tailored operating system combined with the HCI is a viable software imp- lementation to support hardware-based fault-tolerant computing in a space environment.

This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.

This proceedings volume collects review articles that summarize research conducted at the Munich Centre of Advanced Computing (MAC) from 2008 to 2012. The articles address the increasing gap between what should be possible in Computational Science and Engineering due to recent advances in algorithms, hardware, and networks, and what can actually be achieved in practice; they also examine novel computing architectures, where computation itself is a multifaceted process, with hardware awareness or ubiquitous parallelism due to many-core systems being just two of the challenges faced. Topics cover both the methodological aspects of advanced computing (algorithms, parallel computing, data exploration, software engineering) and cutting-edge applications from the fields of chemistry, the geosciences, civil and mechanical engineering, etc., reflecting the highly interdisciplinary nature of the Munich Centre of Advanced Computing.

This in-depth guide to Version 8 SPARC, a high-speed RISC computer chip, provides the reader with the background, design philosophy, high-level features and implementations of this new model. Includes an expanded index of terms for easy reference and a table of synthetic instructions added to the suggested assembly language syntax.

Written by leading experts in the field, this book provides the state-of-the-art in terms of fault tolerant control applicable to civil aircraft. The book consists of five parts and includes online material.

This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.