This issue describes processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

These proceedings describe processing, materials, and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

These proceedings describe processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics: strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

This issue of ¿ECS Transactions¿ describes processing, materials and equipment for CMOS front-end integration including gate stack, source/drain and channel engineering. Topics include strained Si/SiGe and Si/SiGe on insulator; high-mobility channels including III-V¿s, etc.; nanowires and carbon nanotubes; high-k dielectrics, metal and FUSI gate electrodes; doping/annealing for ultra-shallow junctions; low-resistivity contacts; advanced deposition (e.g. ALD, CVD, MBE), RTP, UV, plasma and laser-assisted processes.

Microelectronics is a complex world where many sciences need to collaborate to create nano-objects: we need expertise in electronics, microelectronics, physics, optics and mechanics also crossing into chemistry, electrochemistry, as well as biology, biochemistry and medicine. Chemistry is involved in many fields from materials, chemicals, gases, liquids or salts, the basics of reactions and equilibrium, to the optimized cleaning of surfaces and selective etching of specific layers. In addition, over recent decades, the size of the transistors has been drastically reduced while the functionality of circuits has increased. This book consists of five chapters covering the chemicals and sequences used in processing, from cleaning to etching, the role and impact of their purity, along with the materials used in “Front End Of the Line” which corresponds to the heart and performance of individual transistors, then moving on to the “Back End Of the Line” which is related to the interconnection of all the transistors. Finally, the need for specific functionalization also requires key knowledge on surface treatments and chemical management to allow new applications. Contents 1. Chemistry in the “Front End of the Line” (FEOL): Deposits, Gate Stacks, Epitaxy and Contacts, François Martin, Jean-Michel Hartmann, Véronique Carron and Yannick Le Tiec. 2. Chemistry in Interconnects, Vincent Jousseaume, Paul-Henri Haumesser, Carole Pernel, Jeffery Butterbaugh, Sylvain Maîtrejean and Didier Louis. 3. The Chemistry of Wet Surface Preparation: Cleaning, Etching and Drying, Yannick Le Tiec and Martin Knotter. 4. The Use and Management of Chemical Fluids in Microelectronics, Christiane Gottschalk, Kevin Mclaughlin, Julie Cren, Catherine Peyne and Patrick Valenti. 5. Surface Functionalization for Micro- and Nanosystems: Application to Biosensors, Antoine Hoang, Gilles Marchand, Guillaume Nonglaton, Isabelle Texier-Nogues and Francoise Vinet. About the Authors Yannick Le Tiec is a technical expert at CEA-Leti, Minatec since 2002. He is a CEA-Leti assignee at IBM, Albany (NY) to develop the advanced 14 nm CMOS node and the FDSOI technology. He held different technical positions from the advanced 300 mm SOI CMOS pilot line to different assignments within SOITEC for advanced wafer development and later within INES to optimize solar cell ramp-up and yield. He has been part of the ITRS Front End technical working group at ITRS since 2008.