Abstract: A process-based model (UFET) for deep-submicron bulk-silicon MOSFETs is developed and verified with numerical device simulations and measured data. The charge-based model is physical with accountings for the predominant short-channel (e.g., charge sharing, drain-induced threshold reduction and velocity saturation) and extremely scaled-technology (i.e., energy quantization and polysilicon-gate depletion) effects in MOSFETs. The key to UFET is the characterization of the bias-dependent two-dimensional regions near the source/ drain junctions which can extend over a significant fraction of the metallurgical channel length. When these two-dimensional regions near the junctions are modeled, the physical charge-sheet model can be applied to the remaining "quasi-two- dimensional" channel length to define the channel current and terminal charges, without resorting to empiricism to account for the short-channel effects. Special attention paid to continuity in the derivation of the model formalism yields a physical C-infinity model applicable to analog and digital CMOS circuit design. The small number of physical, process-based parameters simplifies the model calibration, and renders the model suitable for predictive device/circuit simulation, statistical simulations and circuit sensitivity analyses based on known or presumed process variations. Dissertation Discovery Company and University of Florida are dedicated to making scholarly works more discoverable and accessible throughout the world. This dissertation, "A Physical MOSFET Model Applicable to Extremely Scaled CMOS IC Design" by Douglas Aaron Weiser, was obtained from University of Florida and is being sold with permission from the author. A digital copy of this work may also be found in the university's institutional repository, IR@UF. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation.

The essentials of analog circuit design with a unique all-region MOSFET modeling approach.

This is the first book dedicated to the next generation of MOSFET models. Addressed to circuit designers with an in-depth treatment that appeals to device specialists, the book presents a fresh view of compact modeling, having completely abandoned the regional modeling approach.Both an overview of the basic physics theory required to build compact MOSFET models and a unified treatment of inversion-charge and surface-potential models are provided. The needs of digital, analog and RF designers as regards the availability of simple equations for circuit designs are taken into account. Compact expressions for hand analysis or for automatic synthesis, valid in all operating regions, are presented throughout the book. All the main expressions for computer simulation used in the new generation compact models are derived.Since designers in advanced technologies are increasingly concerned with fluctuations, the modeling of fluctuations is strongly emphasized. A unified approach for both space (matching) and time (noise) fluctuations is introduced.

Understand the theory, design and applications of FD/SOI MOSFETs and 3-D FinFETs with this concise and clear guide to FD/UTB transistors. Topics covered include short-channel effects, quantum-mechanical effects, applications of UTB devices to floating-body DRAM and conventional SRAM, and nanoscale UTB CMOS performances.

Modern, large-scale analog integrated circuits (ICs) are essentially composed of metal-oxide semiconductor (MOS) transistors and their interconnections. As technology scales down to deep sub-micron dimensions and supply voltage decreases to reduce power consumption, these complex analog circuits are even more dependent on the exact behavior of each transistor. High-performance analog circuit design requires a very detailed model of the transistor, describing accurately its static and dynamic behaviors, its noise and matching limitations and its temperature variations. The charge-based EKV (Enz-Krummenacher-Vittoz) MOS transistor model for IC design has been developed to provide a clear understanding of the device properties, without the use of complicated equations. All the static, dynamic, noise, non-quasi-static models are completely described in terms of the inversion charge at the source and at the drain taking advantage of the symmetry of the device. Thanks to its hierarchical structure, the model offers several coherent description levels, from basic hand calculation equations to complete computer simulation model. It is also compact, with a minimum number of process-dependant device parameters. Written by its developers, this book provides a comprehensive treatment of the EKV charge-based model of the MOS transistor for the design and simulation of low-power analog and RF ICs. Clearly split into three parts, the authors systematically examine: the basic long-channel intrinsic charge-based model, including all the fundamental aspects of the EKV MOST model such as the basic large-signal static model, the noise model, and a discussion of temperature effects and matching properties; the extended charge-based model, presenting important information for understanding the operation of deep-submicron devices; the high-frequency model, setting out a complete MOS transistor model required for designing RF CMOS integrated circuits. Practising engineers and circuit designers in the semiconductor device and electronics systems industry will find this book a valuable guide to the modelling of MOS transistors for integrated circuits. It is also a useful reference for advanced students in electrical and computer engineering.

Metal Oxide Semiconductor (MOS) transistors are the basic building block ofMOS integrated circuits (I C). Very Large Scale Integrated (VLSI) circuits using MOS technology have emerged as the dominant technology in the semiconductor industry. Over the past decade, the complexity of MOS IC's has increased at an astonishing rate. This is realized mainly through the reduction of MOS transistor dimensions in addition to the improvements in processing. Today VLSI circuits with over 3 million transistors on a chip, with effective or electrical channel lengths of 0. 5 microns, are in volume production. Designing such complex chips is virtually impossible without simulation tools which help to predict circuit behavior before actual circuits are fabricated. However, the utility of simulators as a tool for the design and analysis of circuits depends on the adequacy of the device models used in the simulator. This problem is further aggravated by the technology trend towards smaller and smaller device dimensions which increases the complexity of the models. There is extensive literature available on modeling these short channel devices. However, there is a lot of confusion too. Often it is not clear what model to use and which model parameter values are important and how to determine them. After working over 15 years in the field of semiconductor device modeling, I have felt the need for a book which can fill the gap between the theory and the practice of MOS transistor modeling. This book is an attempt in that direction.