The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system testing.

This book is a single-source solution for anyone who is interested in exploring emerging reconfigurable nanotechnology at the circuit level. It lays down a solid foundation for circuits based on this technology having considered both manual as well as automated design flows. The authors discuss the entire design flow, consisting of both logic and physical synthesis for reconfigurable nanotechnology-based circuits. The authors describe how transistor reconfigurable properties can be exploited at the logic level to have a more efficient circuit design flow, as compared to conventional design flows suited for CMOS. Further, the book provides insights into hardware security features that can be intrinsically developed using the runtime reconfigurable features of this nanotechnology.

Dive into the cutting-edge world of Neuromorphic Computing, a groundbreaking volume that unravels the secrets of brain-inspired computational paradigms. Spanning neuroscience, artificial intelligence, and hardware design, this book presents a comprehensive exploration of neuromorphic systems, empowering both experts and newcomers to embrace the limitless potential of brain-inspired computing. Discover the fundamental principles that underpin neural computation as we journey through the origins of neuromorphic architectures, meticulously crafted to mimic the brain’s intricate neural networks. Unlock the true essence of learning mechanisms – unsupervised, supervised, and reinforcement learning – and witness how these innovations are shaping the future of artificial intelligence.

This book provides a comprehensive overview of security vulnerabilities and state-of-the-art countermeasures using explainable artificial intelligence (AI). Specifically, it describes how explainable AI can be effectively used for detection and mitigation of hardware vulnerabilities (e.g., hardware Trojans) as well as software attacks (e.g., malware and ransomware). It provides insights into the security threats towards machine learning models and presents effective countermeasures. It also explores hardware acceleration of explainable AI algorithms. The reader will be able to comprehend a complete picture of cybersecurity challenges and how to detect them using explainable AI. This book serves as a single source of reference for students, researchers, engineers, and practitioners for designing secure and trustworthy systems.

This proceedings includes original, unpublished, peer-reviewed research papers from the International Conference on Wireless Communications, Networking and Applications (WCNA2022), held in Wuhan, Hubei, China, from December 16 to 18, 2022. The topics covered include but are not limited to wireless communications, networking and applications. The papers showcased here share the latest findings on methodologies, algorithms and applications in communication and network, making the book a valuable asset for professors, researchers, engineers, and university students alike.

Heterogeneous systems on chip (HeSoCs) combine general-purpose, feature-rich multi-core host processors with domain-specific programmable many-core accelerators (PMCAs) to unite versatility with energy efficiency and peak performance. By virtue of their heterogeneity, HeSoCs hold the promise of increasing performance and energy efficiency compared to homogeneous multiprocessors, because applications can be executed on hardware that is designed for them. However, this heterogeneity also increases system complexity substantially. This thesis presents the first research platform for HeSoCs where all components, from accelerator cores to application programming interface, are available under permissive open-source licenses. We begin by identifying the hardware and software components that are required in HeSoCs and by designing a representative hardware and software architecture. We then design, implement, and evaluate four critical HeSoC components that have not been discussed in research at the level required for an open-source implementation: First, we present a modular, topology-agnostic, high-performance on-chip communication platform, which adheres to a state-of-the-art industry-standard protocol. We show that the platform can be used to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end communication fabrics with high degrees of concurrency (e.g., up to 256 independent concurrent transactions). Second, we present a modular and efficient solution for implementing atomic memory operations in highly-scalable many-core processors, which demonstrates near-optimal linear throughput scaling for various synthetic and real-world workloads and requires only 0.5 kGE per core. Third, we present a hardware-software solution for shared virtual memory that avoids the majority of translation lookaside buffer misses with prefetching, supports parallel burst transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our work improves accelerator performance for memory-intensive kernels by up to 4×. Fourth, we present a software toolchain for mixed-data-model heterogeneous compilation and OpenMP offloading. Our work enables transparent memory sharing between a 64-bit host processor and a 32-bit accelerator at overheads below 0.7 % compared to 32-bit-only execution. Finally, we combine our contributions to a research platform for state-of-the-art HeSoCs and demonstrate its performance and flexibility.