The International Integrated Reliability Workshop provides a forum for sharing new approaches to achieve and maintain microelectronic component reliability. Topics include: contributors to failure; waver level reliability; building in reliability; and reliability test structures.

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.

This book takes a holistic approach to reliability engineering for electrical and electronic systems by looking at the failure mechanisms, testing methods, failure analysis, characterisation techniques and prediction models that can be used to increase reliability for a range of devices. The text describes the reliability behavior of electrical and electronic systems. It takes an empirical scientific approach to reliability engineering to facilitate a greater understanding of operating conditions, failure mechanisms and the need for testing for a more realistic characterisation. After introducing the fundamentals and background to reliability theory, the text moves on to describe the methods of reliability analysis and charactersation across a wide range of applications. Takes a holistic approach to reliability engineering Looks at the failure mechanisms, testing methods, failure analysis, characterisation techniques and prediction models that can be used to increase reliability Facilitates a greater understanding of operating conditions, failure mechanisms and the need for testing for a more realistic characterisation

After many decades, the scaling of silicon dioxide based field-effect transistors has reached insurmountable physical limits due unintentional high gate leakage currents for gate oxide thicknesses below 2 nm. The introduction of high-k metal gate stacks guaranteed the trend towards smaller transistor dimensions. The implementation of HfO2, as high-k dielectric, also lead to a substantial number of manufacturing and reliability challenges. The deterioration of the gate oxide properties under thermal and electric stress jeopardizes the circuit operation and hence needs to be comprehensively understood. As a starting point, 6T static random access memory cells were used to identify the different single device operating conditions. The strongest deterioration of the gate stack was found for nMOS devices under positive bias temperature instability (PBTI) stress, resulting in a severe threshold voltage shift and increased gate leakage current. A detailed investigation of physical origin and temperature and voltage dependency was done. The reliability issues were caused by the electron trapping into already existing HfO2 oxygen vacancies. The oxygen vacancies reside in different charge states depending on applied stress voltages. This in return also resulted in a strong threshold voltage and gate current relaxation after stress was cut off. The reliability assessment using constant voltage stress does not reflect realistic circuit operation which can result in a changed degradation behaviour. Therefore, the constant voltage stress measurement were extended by considering CMOS operational constraints, where it was found that the supply voltage frequently switches between the gate and drain terminal. The additional drain (off-state) bias lead to an increased Vt relaxation in comparison to zero bias voltage. The off-state influence strongly depended on the gate length and became significant for short channel devices. The influence of the off-state bias on the dielectric breakdown was studied and compared to the standard assessment methods. Different wear-out mechanisms for drain-only and alternating gate and drain stress were verified. Under drain-only stress, the dielectric breakdown was caused by hot carrier degradation. The lifetime was correlated with the device length and amount of subthreshold leakage. The gate oxide breakdown under alternating gate and o-state stress was caused by the continuous trapping and detrapping behaviour of high-k metal gate devices.